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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 01/49] hw/net/fsl_etsec: validate FCB offsets in process_tx_fcb()
Date: Mon,  6 Jul 2026 11:37:04 +0100	[thread overview]
Message-ID: <20260706103752.320511-2-peter.maydell@linaro.org> (raw)
In-Reply-To: <20260706103752.320511-1-peter.maydell@linaro.org>

From: Feifan Qian <bea1e@proton.me>

The TX Frame Control Block (FCB) is prepended to a TX frame when
BD_TX_TOEUN is set. It contains two guest-controlled u8 offset
fields that process_tx_fcb() uses to locate L3/L4 headers within
the frame buffer:

  l3_header_offset = FCB byte 3 (0..255)
  l4_header_offset = FCB byte 2 (0..255)

These offsets are applied without any bounds check. When the
UDP-no-CTU branch is taken, the function writes zero to
l4_header[6] and l4_header[7]. With both offsets set to 0xFF the
write target is:

  tx_buffer + 8 + 255 + 255 + 6/7 = tx_buffer + 525

A malicious guest can therefore corrupt up to 509 bytes of heap
memory beyond a minimally-sized (16 B) TX frame.

Fix: reject the frame and log a guest error when the minimum
required buffer length

  8 (FCB) + l3_header_offset + l4_header_offset + 8

exceeds tx_buffer_len. Move the l3_header and l4_header pointer
declarations past the new guard so that out-of-bounds pointers
are never materialised.

Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3517
Signed-off-by: Feifan Qian <bea1e@proton.me>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/net/fsl_etsec/rings.c | 27 +++++++++++++++++++++------
 1 file changed, 21 insertions(+), 6 deletions(-)

diff --git a/hw/net/fsl_etsec/rings.c b/hw/net/fsl_etsec/rings.c
index 6d2bf71b52..c8fc5d55d1 100644
--- a/hw/net/fsl_etsec/rings.c
+++ b/hw/net/fsl_etsec/rings.c
@@ -177,16 +177,31 @@ static void tx_padding_and_crc(eTSEC *etsec, uint32_t min_frame_len)
 static void process_tx_fcb(eTSEC *etsec)
 {
     uint8_t flags = (uint8_t)(*etsec->tx_buffer);
-    /* L3 header offset from start of frame */
+    /* L3 header offset from start of frame (FCB byte 3) */
     uint8_t l3_header_offset = (uint8_t)*(etsec->tx_buffer + 3);
-    /* L4 header offset from start of L3 header */
+    /* L4 header offset from start of L3 header (FCB byte 2) */
     uint8_t l4_header_offset = (uint8_t)*(etsec->tx_buffer + 2);
-    /* L3 header */
-    uint8_t *l3_header = etsec->tx_buffer + 8 + l3_header_offset;
-    /* L4 header */
-    uint8_t *l4_header = l3_header + l4_header_offset;
+    uint8_t *l3_header;
+    uint8_t *l4_header;
     int csum = 0;
 
+    /*
+     * Validate FCB header offsets before pointer arithmetic. The highest
+     * byte accessed is l4_header[7], at offset
+     *   8 (FCB size) + l3_header_offset + l4_header_offset + 7
+     * from tx_buffer. Drop the frame if this exceeds the buffer length.
+     */
+    if (etsec->tx_buffer_len < 8u + l3_header_offset + l4_header_offset + 8u) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "eTSEC: FCB offsets exceed frame length, dropping\n");
+        return;
+    }
+
+    /* L3 header */
+    l3_header = etsec->tx_buffer + 8 + l3_header_offset;
+    /* L4 header */
+    l4_header = l3_header + l4_header_offset;
+
     /* if packet is IP4 and IP checksum is requested */
     if (flags & FCB_TX_IP && flags & FCB_TX_CIP) {
         csum |= CSUM_IP;
-- 
2.43.0



  reply	other threads:[~2026-07-06 10:39 UTC|newest]

Thread overview: 53+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-06 10:37 [PULL 00/49] target-arm queue Peter Maydell
2026-07-06 10:37 ` Peter Maydell [this message]
2026-07-06 10:37 ` [PULL 02/49] hw/arm/smmuv3-accel: Fix veventq read returning true on EAGAIN/EINTR Peter Maydell
2026-07-06 10:37 ` [PULL 03/49] target/arm: Only evaluate SCR_EL3.PIEN if ARM_FEATURE_EL3 is present Peter Maydell
2026-07-06 10:37 ` [PULL 04/49] target/arm/tcg: Implement new instructions for FPRCVT Peter Maydell
2026-07-06 10:37 ` [PULL 05/49] target/arm/tcg: Allow vector FP conversions with FPRCVT Peter Maydell
2026-07-06 10:37 ` [PULL 06/49] target/arm/tcg/cpu64.c: Add FEAT_FPRCVT to cpu_max Peter Maydell
2026-07-06 10:37 ` [PULL 07/49] linux-user/aarch64/elfload.c: Add FPRCVT Peter Maydell
2026-07-06 10:37 ` [PULL 08/49] docs/system/arm: Add FEAT_FPRCVT to A-profile support Peter Maydell
2026-07-06 10:37 ` [PULL 09/49] tests/tcg/arm: Tests for new FPRCVT instructions Peter Maydell
2026-07-07 18:59   ` Pierrick Bouvier
2026-07-07 21:53     ` Pierrick Bouvier
2026-07-06 10:37 ` [PULL 10/49] target/arm: Implement and enable FEAT_SSVE_FEXPA for -cpu max Peter Maydell
2026-07-06 10:37 ` [PULL 11/49] hw/arm: use cortex-a9 mpcore base for CBAR on npcm7xx machines Peter Maydell
2026-07-06 10:37 ` [PULL 12/49] tests/functional: update anacapa-bmc image Peter Maydell
2026-07-06 10:37 ` [PULL 13/49] target/arm: do not clear halting reason in has_work helper Peter Maydell
2026-07-06 10:37 ` [PULL 14/49] target/arm: ensure we create the wxft_timer for all modes Peter Maydell
2026-07-06 10:37 ` [PULL 15/49] target/arm: implements SEV/SEVL " Peter Maydell
2026-07-06 10:37 ` [PULL 16/49] target/arm: enable WFE sleeping for A-profile Peter Maydell
2026-07-06 10:37 ` [PULL 17/49] target/arm: implement WFET Peter Maydell
2026-07-06 10:37 ` [PULL 18/49] docs/specs/fw_cfg: Document all architecture register layouts Peter Maydell
2026-07-06 10:37 ` [PULL 19/49] hw/nvram/fw_cfg: Enforce standard layout for fw_cfg_init_mem_dma() Peter Maydell
2026-07-06 10:37 ` [PULL 20/49] hw/nvram/fw_cfg: Enforce standard layout for x86 fw_cfg I/O ports Peter Maydell
2026-07-06 10:37 ` [PULL 21/49] hw/nvram/fw_cfg: Remove support for I/O port fw_cfg without DMA Peter Maydell
2026-07-06 10:37 ` [PULL 22/49] hw/nvram/fw_cfg: Document fw_cfg_init_mem_nodma() Peter Maydell
2026-07-06 10:37 ` [PULL 23/49] hw/misc/imx_ccm: Replace DPRINTF with trace events Peter Maydell
2026-07-06 10:37 ` [PULL 24/49] hw/misc/imx25_ccm: " Peter Maydell
2026-07-06 10:37 ` [PULL 25/49] hw/misc/imx31_ccm: " Peter Maydell
2026-07-06 10:37 ` [PULL 26/49] target/arm/hvf: seed NO_RAW ID registers from isar.idregs[] on vCPU init Peter Maydell
2026-07-06 10:37 ` [PULL 27/49] hw/nvram: add load_image_to_fw_cfg_file() Peter Maydell
2026-07-06 10:37 ` [PULL 28/49] hw/i386: switch shim loading to load_image_to_fw_cfg_file Peter Maydell
2026-07-06 10:37 ` [PULL 29/49] hw/arm: add support for shim loading Peter Maydell
2026-07-06 10:37 ` [PULL 30/49] docs/system/arm: Document Zynq Buildroot boot Peter Maydell
2026-07-06 10:37 ` [PULL 31/49] target/arm: Implement FMOP4 (non-widening) for float32 Peter Maydell
2026-07-06 10:37 ` [PULL 32/49] target/arm: Implement FMOP4 (non-widening) for float16 Peter Maydell
2026-07-06 10:37 ` [PULL 33/49] target/arm: Implement FMOP4 (non-widening) for float64 Peter Maydell
2026-07-06 10:37 ` [PULL 34/49] target/arm: Implement BFMOP4 (non-widening) Peter Maydell
2026-07-06 10:37 ` [PULL 35/49] target/arm: Implement BFMOP4 (widening) Peter Maydell
2026-07-06 10:37 ` [PULL 36/49] target/arm: Implement FMOP4 (widening, 2-way fp16 to fp32) Peter Maydell
2026-07-06 10:37 ` [PULL 37/49] target/arm: Implement FMOP4 (widening, 4-way fp8 " Peter Maydell
2026-07-06 10:37 ` [PULL 38/49] target/arm: Implement FMOP4A (widening, 2-way, FP8 to FP16) Peter Maydell
2026-07-06 10:37 ` [PULL 39/49] target/arm: Implement SMOP4[AS] (2-way) Peter Maydell
2026-07-06 10:37 ` [PULL 40/49] target/arm: Implement SMOP4[AS] (4-way) Peter Maydell
2026-07-06 10:37 ` [PULL 41/49] target/arm: Implement SUMOP4[AS] Peter Maydell
2026-07-06 10:37 ` [PULL 42/49] target/arm: Implement UMOP4[AS] (2-way) Peter Maydell
2026-07-06 10:37 ` [PULL 43/49] target/arm: Implement UMOP4[AS] (4-way) Peter Maydell
2026-07-06 10:37 ` [PULL 44/49] target/arm: Implement USMOP4[AS] Peter Maydell
2026-07-06 10:37 ` [PULL 45/49] target/arm: Enable FEAT_SME_MOP4 for -cpu max Peter Maydell
2026-07-06 10:37 ` [PULL 46/49] target/arm: Separate out Neon from VFP access checks Peter Maydell
2026-07-06 10:37 ` [PULL 47/49] target/arm: Separate syndrome functions for A32 and A64 Peter Maydell
2026-07-06 10:37 ` [PULL 48/49] target/arm: Report correct syndrome to AArch32 EL2 for trapped Neon/VFP insns Peter Maydell
2026-07-06 10:37 ` [PULL 49/49] target/arm: Define fields for NSACR Peter Maydell
2026-07-07  5:04 ` [PULL 00/49] target-arm queue Stefan Hajnoczi

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