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Tue, 7 Jul 2026 02:40:31 -0500 From: James Lin To: CC: , , , , James Lin Subject: [PATCH i-g-t] tests/amdgpu: Tolerate bandwidth-limited MPO scale combinations in mpo-scale Date: Tue, 7 Jul 2026 15:42:44 +0800 Message-ID: <20260707074312.3492-1-PingLei.Lin@amd.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA52:EE_|PH7PR12MB6717:EE_ X-MS-Office365-Filtering-Correlation-Id: 357a95ab-0e8d-4eb1-ec2d-08dedbfb09ee X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|23010399003|1800799024|82310400026|376014|36860700016|6133799003|18002099003|11063799006|56012099006; X-Microsoft-Antispam-Message-Info: tI3LjUoahyCIz6b0zWoOzEU6JLL8UJbaCw/rpmJgjohiv6oK3NCgS7wPuA/Z2OEWmzpaRbxcpFHbLE1yNM2gXpz0NXfuq1OYout5rNFFQY/akKTgnHsyEM5DEqZZ5dR04urQCzoyNPI65uAliXll3W66EljV5YdVXIG6Kwa+kuPFr+/SUl2rPLiWJx0wisrokJjzPknCfl/6QI7U/Vuj9peDvqVsV0Alj8igmKzXk7ReL+FqijuQ4L91JD9arFxBrF4I3htUJTSt7LtnG3iy8oCCyMx1EPSg0N6NbBQxWg9Ii2rkjjXHYxIAqp7rNjg4vP+kHt7J+3dJviNDKzXWwqOQQf6ag4IQg7Y8G2TPjLmliCfRvTBPS8PnMLLUwsacZsXN7Wnz2PNSgPdYPMaqfV36EQregh3k9L/dxUhPttgYRCLlMAeR29Lr/+Rz9fZnZ9UZCPqXlJ/DCb0Z1NA1MciVMI3wDi5MOwWPHMMduEsAlKVyUUvMIhTNTNjQK8yriPbe8BnjMk60pk+Z31g1K48wr0EcA54gNsMZsjcLhJNMThlL4ziNhlGSw6eN2lUJDvUnSgB7jTqvUm7XvzbTCaIzgx/UOR64fAIgEIKGjKRK8NE70F3f4RO+cZsRqiSK+Jk0sK65olQHvMrGHaj2wc45cxs2Yk4rGdULsF07hcVpXJ4loABpTTXkLMh3a623CFxRI4cOKLSmm2cNuxqP0w== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA52.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6717 X-BeenThere: igt-dev@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development mailing list for IGT GPU Tools List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: igt-dev-bounces@lists.freedesktop.org Sender: "igt-dev" [Why] amd_plane@mpo-scale-* iterates every source size (up to 4K) and scale factor and performs a hard igt_display_commit_atomic() for each MPO arrangement. Downscaling still reads the full source surface, so a heavily downscaled large source (e.g. 4K at 0.30x) costs as much display read bandwidth as a full-size plane. Combined with the full-screen overlay and DSC at high refresh rates, the configuration can legitimately exceed the display controller's bandwidth and be rejected by the driver (DC_FAIL_BANDWIDTH_VALIDATE -> -EINVAL). That is a hardware limit, not a scaler defect, but the hard commit turned the legitimate -EINVAL into an unparsable test failure (the run aborted during commit with no result line emitted). [How] Replace the hard commit in test_plane with igt_display_try_commit_atomic and tolerate only a legitimate rejection: a downscale (displayed area smaller than the source surface) rejected specifically with -EINVAL. Any other errno, or a failing upscale, still fails the test. Bound the number of tolerated skips with MPO_MAX_BW_SKIPS so an unexpectedly large number of rejections is treated as a real regression rather than isolated bandwidth limits. Skipped combinations restore the reference primary plane so subsequent iterations start from a committable state; configurations that do commit are still fully CRC-validated. Signed-off-by: James Lin --- tests/amdgpu/amd_plane.c | 57 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/tests/amdgpu/amd_plane.c b/tests/amdgpu/amd_plane.c index 9a08f8e29..0e849b9b4 100644 --- a/tests/amdgpu/amd_plane.c +++ b/tests/amdgpu/amd_plane.c @@ -28,6 +28,14 @@ IGT_TEST_DESCRIPTION("Tests for Multi Plane Overlay for single and dual displays /* Maximum pipes on any AMD ASIC. */ #define MAX_PIPES 6 + +/* + * Upper bound on how many scale/source combinations may be skipped because + * the driver legitimately rejects them on display-bandwidth grounds + * (DC_FAIL_BANDWIDTH_VALIDATE). Empirically only the heaviest downscales of + * the largest sources hit this; many more than that means a real regression. + */ +#define MPO_MAX_BW_SKIPS 4 #define DISPLAYS_TO_TEST 2 /* (De)gamma LUT. */ @@ -50,6 +58,7 @@ typedef struct data { int w[MAX_PIPES]; int h[MAX_PIPES]; int fd; + int bw_skips; } data_t; static const drmModeModeInfo test_mode_1 = { @@ -382,6 +391,7 @@ static void test_plane(data_t *data, int n, int x, int y, double dw, double dh, igt_crc_t test_crc; igt_display_t *display = &data->display; + int ret; /* Reference: */ @@ -404,7 +414,48 @@ static void test_plane(data_t *data, int n, int x, int y, double dw, double dh, igt_plane_set_position(data->primary[n], x, y); igt_plane_set_size(data->primary[n], dw, dh); - igt_display_commit_atomic(display, 0, 0); + /* + * Downscaling reads the full source surface, so a heavily downscaled + * large (e.g. 4K) MPO source costs as much display read bandwidth as a + * full-size plane. Combined with the full-screen overlay and (on some + * panels) DSC at high refresh rates, the resulting configuration can + * legitimately exceed the display controller's bandwidth and be + * rejected by the driver (DC_FAIL_BANDWIDTH_VALIDATE -> -EINVAL). That + * is a hardware limit, not a scaler defect, so skip such combinations + * rather than failing the test. Configurations that do commit are still + * fully CRC-validated below. + */ + ret = igt_display_try_commit_atomic(display, 0, NULL); + if (ret != 0) { + /* + * Only tolerate a *downscale* (displayed area smaller than the + * source surface) rejected specifically with -EINVAL, which is + * the DC_FAIL_BANDWIDTH_VALIDATE path. Any other errno, or a + * failing upscale, is a real bug and must fail the test. + */ + bool downscale = (dw < fbc[n].test_primary.width || + dh < fbc[n].test_primary.height); + + igt_assert_f(downscale && ret == -EINVAL, + "atomic commit rejected unexpectedly (ret=%d, downscale=%d): n=%d dw=%.0f dh=%.0f src=%dx%d pw=%d ph=%d\n", + ret, downscale, n, dw, dh, + fbc[n].test_primary.width, + fbc[n].test_primary.height, pw, ph); + + data->bw_skips++; + igt_assert_f(data->bw_skips <= MPO_MAX_BW_SKIPS, + "too many MPO scale combinations skipped (%d > %d); likely a real regression, not isolated bandwidth limits\n", + data->bw_skips, MPO_MAX_BW_SKIPS); + + igt_info("Skipping unsupported scale (likely display bandwidth limit): n=%d dw=%.0f dh=%.0f pw=%d ph=%d (skip %d/%d)\n", + n, dw, dh, pw, ph, data->bw_skips, MPO_MAX_BW_SKIPS); + igt_plane_set_fb(data->overlay[n], NULL); + igt_plane_set_fb(data->primary[n], &fbc[n].ref_primary); + igt_plane_set_position(data->primary[n], 0, 0); + igt_plane_set_size(data->primary[n], pw, ph); + igt_display_commit_atomic(display, 0, 0); + return; + } igt_pipe_crc_collect_crc(data->pipe_crc[n], &test_crc); igt_plane_set_fb(data->overlay[n], NULL); @@ -616,6 +667,8 @@ static void test_display_mpo(data_t *data, enum test test, uint32_t format, int test_init(data); + data->bw_skips = 0; + /* Skip test if we don't have 2 overlay planes */ if (test == MPO_MULTI_OVERLAY) igt_skip_on(!data->overlay2[0]); @@ -662,6 +715,8 @@ static void test_display_mpo(data_t *data, enum test test, uint32_t format, int for (int n = 0; n < display_count; n++) igt_pipe_crc_collect_crc(data->pipe_crc[n], &fb[n].ref_crc); + igt_kmsg(KMSG_WARNING "MPOSCALE setup done (ref crc collected), entering scaling loop\n"); + for (int i = 0; i < ARRAY_SIZE(videos); ++i) { /* Video(mpo) should be in the middle when it transitions between displays. This -- 2.43.0