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Wed, 8 Jul 2026 09:20:24 +0000 From: Jamin Lin To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Kane Chen , Andrew Jeffery , Joel Stanley , Pierrick Bouvier , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: Jamin Lin , Troy Lee Subject: [PATCH v5 00/10] Add SSP/TSP power control and DRAM remap support for AST2700 Thread-Topic: [PATCH v5 00/10] Add SSP/TSP power control and DRAM remap support for AST2700 Thread-Index: AQHdDrsB0PfBWMtPU0KIoukeQI21FA== Date: Wed, 8 Jul 2026 09:20:24 +0000 Message-ID: <20260708092023.3826159-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: TYZPR06MB4980:EE_|SEYPR06MB6311:EE_ x-ms-office365-filtering-correlation-id: cf9e5d7d-44cd-4aa1-809f-08dedcd22476 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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envelope-from=jamin_lin@aspeedtech.com; helo=SEYPR02CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org This series improves AST2700 platform support by aligning SSP/TSP=0A= power and reset behavior with hardware, and enabling DRAM remapping=0A= required for proper firmware boot flow.=0A= =0A= This series depends on:=0A= [v2,0/8] Refactor AST2700 SCU preparation for coprocessors=0A= https://patchwork.kernel.org/project/qemu-devel/cover/20260707060919.350637= -1-jamin_lin@aspeedtech.com/=0A= =0A= v1:=0A= 1. The changes move DRAM/SDMC initialization earlier to support memory=0A= aliasing, add DRAM aliases for SSP/TSP SDRAM remap, and implement=0A= SSP/TSP reset, power-on, and remap controls via SCU registers.=0A= 2. With these updates, SSP and TSP can be booted via PSP and load their= =0A= binaries from DRAM. Functional tests and documentation are updated=0A= accordingly.=0A= =0A= v2:=0A= Fix "make check" failure caused by both AST2700 and AST1700 realizing the= same=0A= TYPE_AST2700_SCU model.=0A= =0A= v3:=0A= 1. Drop "Move DRAM and SDMC initialization earlier to support memory alias= ing"=0A= 2. Support SPI/FMC FIFO Mode=0A= 3. Add unimplemented devices=0A= =0A= v4:=0A= 1. Introduce Aspeed2700SCU subclass and separate from generic SCU.=0A= 2. Add separate reset handler for AST2700 SCUIO=0A= 3. Add AST2700 SCUIO RNG control and data registers=0A= 4. Share single SCUIO instance across PSP, SSP, and TSP=0A= 5. Fix AST2700 FC hardware strap settings=0A= =0A= v5:=0A= 1. To speed up the review process, move the following patches into a separ= ate =0A= patch series, as they are not directly related to the main topic of thi= s series:=0A= =0A= [v4,01/21] hw/misc/aspeed_scu: Introduce Aspeed2700SCU subclass and sep= arate from generic SCU=0A= [v4,02/21] hw/misc/aspeed_scu: Add separate reset handler for AST2700 S= CUIO=0A= [v4,11/21] hw/arm/ast27x0: Share FMC controller with SSP and TSP=0A= [v4,12/21] hw/arm/aspeed_ast27x0: Add unimplemented Privilege Controlle= r MMIO regions for SSP/TSP (Merged)=0A= [v4,13/21] hw/arm/aspeed_ast27x0: Add unimplemented OTP controller MMIO= regions for SSP/TSP (Merged)=0A= [v4,14/21] hw/block/m25p80: Implement volatile status register write en= able for Winbond=0A= [v4,15/21] hw/ssi/aspeed_smc: Add Data FIFO-based flash access support = for AST2700=0A= [v4,16/21] hw/misc/aspeed_scu: Drop noisy unhandled read logs for AST27= 00 SCU/SCUIO (Merged)=0A= [v4,17/21] hw/misc/aspeed_scu: Add AST2700 SCUIO RNG control and data r= egisters (Merged)=0A= [v4,18/21] hw/arm/ast27x0: Share single SCUIO instance across PSP, SSP,= and TSP=0A= [v4,19/21] hw/arm/aspeed_ast27x0-fc: Fix hardware strap settings (Merge= d)=0A= =0A= 2. Add memory_region_transaction_begin() and memory_region_transaction_co= mmit()=0A= to protect the transaction.=0A= =0A= Jamin Lin (10):=0A= hw/arm/ast27x0: Start SSP in powered-off state to match hardware=0A= behavior=0A= hw/arm/ast27x0: Start TSP in powered-off state to match hardware=0A= behavior=0A= hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap=0A= hw/arm/ast27x0: Add DRAM alias for TSP SDRAM remap=0A= hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU=0A= registers=0A= hw/misc/aspeed_scu: Implement TSP reset and power-on control via SCU=0A= registers=0A= hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap=0A= hw/misc/aspeed_scu: Add SCU support for TSP SDRAM remap=0A= tests/functional/aarch64/test_aspeed_ast2700fc: Boot SSP/TSP via PSP=0A= and load binaries from DRAM=0A= docs: Add support vbootrom and update Manual boot for ast2700fc=0A= =0A= docs/system/arm/aspeed.rst | 42 ++-=0A= include/hw/misc/aspeed_scu.h | 5 +=0A= hw/arm/aspeed_ast27x0-fc.c | 4 +=0A= hw/arm/aspeed_ast27x0-ssp.c | 13 +=0A= hw/arm/aspeed_ast27x0-tsp.c | 10 +=0A= hw/arm/aspeed_ast27x0.c | 6 +=0A= hw/misc/aspeed_scu.c | 285 ++++++++++++++++++=0A= .../aarch64/test_aspeed_ast2700fc.py | 29 +-=0A= 8 files changed, 374 insertions(+), 20 deletions(-)=0A= =0A= -- =0A= 2.43.0=0A=