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Wed, 8 Jul 2026 09:20:27 +0000 From: Jamin Lin To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Kane Chen , Andrew Jeffery , Joel Stanley , Pierrick Bouvier , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: Jamin Lin , Troy Lee Subject: [PATCH v5 02/10] hw/arm/ast27x0: Start TSP in powered-off state to match hardware behavior Thread-Topic: [PATCH v5 02/10] hw/arm/ast27x0: Start TSP in powered-off state to match hardware behavior Thread-Index: AQHdDrsDdM4aXwddqUmi7MxGdtdIog== Date: Wed, 8 Jul 2026 09:20:27 +0000 Message-ID: <20260708092023.3826159-3-jamin_lin@aspeedtech.com> References: <20260708092023.3826159-1-jamin_lin@aspeedtech.com> In-Reply-To: <20260708092023.3826159-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: TYZPR06MB4980:EE_|SEYPR06MB6311:EE_ x-ms-office365-filtering-correlation-id: aa6eb795-f0ff-4aaa-c317-08dedcd22632 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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envelope-from=jamin_lin@aspeedtech.com; helo=SEYPR02CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org In the previous design, both the PSP and TSP were started together during= =0A= SoC initialization. However, on real hardware, the TSP begins in a powered-= off=0A= state. The typical boot sequence involves the PSP powering up first, loadin= g=0A= the TSP firmware binary into shared memory via DRAM remap, and then releasi= ng=0A= the TSP reset and enabling it through SCU control registers.=0A= =0A= To more accurately model this behavior in QEMU, this commit sets the=0A= "start-powered-off" property for the TSP's ARMv7M core. This change ensures= =0A= the TSP remains off until explicitly enabled via the SCU, simulating the=0A= real-world flow where the PSP controls TSP boot through SCU interaction.=0A= =0A= Signed-off-by: Jamin Lin =0A= ---=0A= hw/arm/aspeed_ast27x0-tsp.c | 7 +++++++=0A= 1 file changed, 7 insertions(+)=0A= =0A= diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c=0A= index 39ba062a20..4212e7bd4c 100644=0A= --- a/hw/arm/aspeed_ast27x0-tsp.c=0A= +++ b/hw/arm/aspeed_ast27x0-tsp.c=0A= @@ -192,6 +192,13 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState = *dev_soc, Error **errp)=0A= qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);=0A= object_property_set_link(OBJECT(&a->armv7m), "memory",=0A= OBJECT(s->memory), &error_abort);=0A= + /*=0A= + * The TSP starts in a powered-down state and can be powered up=0A= + * by setting the TSP Control Register through the SCU=0A= + * (System Control Unit)=0A= + */=0A= + object_property_set_bool(OBJECT(&a->armv7m), "start-powered-off", true= ,=0A= + &error_abort);=0A= sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);=0A= =0A= /* SDRAM */=0A= -- =0A= 2.43.0=0A=