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([2a0a:ef40:ea3:3f01:2e0:4cff:fe68:285]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c15ad9bcc26sm357653666b.34.2026.07.08.10.58.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jul 2026 10:59:00 -0700 (PDT) From: Dawid Olesinski To: Herbert Xu , "David S . Miller" , Rob Herring , Krzysztof Kozlowski Cc: Conor Dooley , Heiko Stuebner , Corentin Labbe , linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Dawid Olesinski Subject: [PATCH v2 1/4] dt-bindings: crypto: rockchip: Add RK356x/RK3588 crypto engine binding Date: Wed, 8 Jul 2026 18:58:22 +0100 Message-ID: <20260708175837.1718437-2-dawidro@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260708175837.1718437-1-dawidro@gmail.com> References: <20260708175837.1718437-1-dawidro@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add a YAML device tree binding for the Rockchip second-generation (V2) cryptographic hardware accelerator present on the RK3568 and RK3588 SoCs. The IP block exposes AES-ECB, AES-CBC, AES-XTS block ciphers, SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, MD5, and SM3 hash algorithms, each with a hardware DMA engine controlled via linked-list descriptors. The binding covers two compatible strings: - rockchip,rk3568-crypto: clocks and resets are driven directly by the non-secure CRU (accessible to Linux at EL1). - rockchip,rk3588-crypto: clocks and resets live in SECURECRU, a register bank sandboxed to TrustZone. Linux must request them through the ARM SCMI firmware interface (scmi_clk / scmi_reset), as direct MMIO access to SECURECRU from EL1 triggers a bus fault. Signed-off-by: Dawid Olesinski --- .../crypto/rockchip,rk3588-crypto.yaml | 75 +++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml diff --git a/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml b/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml new file mode 100644 index 000000000000..fc09f21b0654 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/rockchip,rk3588-crypto.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip cryptographic offloader + +maintainers: + - Heiko Stuebner + - Corentin Labbe + - Dawid Olesinski + +properties: + compatible: + enum: + - rockchip,rk3568-crypto + - rockchip,rk3588-crypto + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Core clock for the crypto IP internal logic + - description: AXI interconnect clock interface + - description: AHB interface clock + + clock-names: + items: + - const: core + - const: aclk + - const: hclk + + resets: + maxItems: 1 + + reset-names: + items: + - const: core + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + +additionalProperties: false + +examples: + - | + #include + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + crypto@fe370000 { + compatible = "rockchip,rk3588-crypto"; + reg = <0x0 0xfe370000 0x0 0x2000>; + interrupts = ; + clocks = <&scmi_clk SCMI_CRYPTO_CORE>, <&scmi_clk SCMI_ACLK_SECURE_NS>, + <&scmi_clk SCMI_HCLK_SECURE_NS>; + clock-names = "core", "aclk", "hclk"; + resets = <&scmi_reset SCMI_SRST_CRYPTO_CORE>; + reset-names = "core"; + }; + }; -- 2.47.3 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4D0B4C44501 for ; Wed, 8 Jul 2026 17:59:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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([2a0a:ef40:ea3:3f01:2e0:4cff:fe68:285]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c15ad9bcc26sm357653666b.34.2026.07.08.10.58.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jul 2026 10:59:00 -0700 (PDT) From: Dawid Olesinski To: Herbert Xu , "David S . Miller" , Rob Herring , Krzysztof Kozlowski Cc: Conor Dooley , Heiko Stuebner , Corentin Labbe , linux-crypto@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Dawid Olesinski Subject: [PATCH v2 1/4] dt-bindings: crypto: rockchip: Add RK356x/RK3588 crypto engine binding Date: Wed, 8 Jul 2026 18:58:22 +0100 Message-ID: <20260708175837.1718437-2-dawidro@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260708175837.1718437-1-dawidro@gmail.com> References: <20260708175837.1718437-1-dawidro@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260708_105902_674196_72BDEAA4 X-CRM114-Status: GOOD ( 14.05 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Add a YAML device tree binding for the Rockchip second-generation (V2) cryptographic hardware accelerator present on the RK3568 and RK3588 SoCs. The IP block exposes AES-ECB, AES-CBC, AES-XTS block ciphers, SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, MD5, and SM3 hash algorithms, each with a hardware DMA engine controlled via linked-list descriptors. The binding covers two compatible strings: - rockchip,rk3568-crypto: clocks and resets are driven directly by the non-secure CRU (accessible to Linux at EL1). - rockchip,rk3588-crypto: clocks and resets live in SECURECRU, a register bank sandboxed to TrustZone. Linux must request them through the ARM SCMI firmware interface (scmi_clk / scmi_reset), as direct MMIO access to SECURECRU from EL1 triggers a bus fault. Signed-off-by: Dawid Olesinski --- .../crypto/rockchip,rk3588-crypto.yaml | 75 +++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml diff --git a/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml b/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml new file mode 100644 index 000000000000..fc09f21b0654 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/rockchip,rk3588-crypto.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/rockchip,rk3588-crypto.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip cryptographic offloader + +maintainers: + - Heiko Stuebner + - Corentin Labbe + - Dawid Olesinski + +properties: + compatible: + enum: + - rockchip,rk3568-crypto + - rockchip,rk3588-crypto + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Core clock for the crypto IP internal logic + - description: AXI interconnect clock interface + - description: AHB interface clock + + clock-names: + items: + - const: core + - const: aclk + - const: hclk + + resets: + maxItems: 1 + + reset-names: + items: + - const: core + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + +additionalProperties: false + +examples: + - | + #include + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + crypto@fe370000 { + compatible = "rockchip,rk3588-crypto"; + reg = <0x0 0xfe370000 0x0 0x2000>; + interrupts = ; + clocks = <&scmi_clk SCMI_CRYPTO_CORE>, <&scmi_clk SCMI_ACLK_SECURE_NS>, + <&scmi_clk SCMI_HCLK_SECURE_NS>; + clock-names = "core", "aclk", "hclk"; + resets = <&scmi_reset SCMI_SRST_CRYPTO_CORE>; + reset-names = "core"; + }; + }; -- 2.47.3 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip