From: sashiko-bot@kernel.org
To: "Srirangan Madhavan" <smadhavan@nvidia.com>
Cc: linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH v9 04/11] cxl: Cache endpoint decoder settings during PCI enumeration
Date: Thu, 09 Jul 2026 01:17:53 +0000 [thread overview]
Message-ID: <20260709011753.9867E1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260709010304.680422-5-smadhavan@nvidia.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Enabling PCI_COMMAND_MEMORY and mapping unassigned BARs during early PCI enumeration causes severe resource conflicts and system instability.
- [Medium] Mixing goto-based error handling with scope-based cleanup helpers (`scoped_guard()`), leading to a logical fall-through bug.
--
--- Patch [4]: [PATCH v9 04/11] cxl: Cache endpoint decoder settings during PCI enumeration ---
commit 64ea438bc1dd54d340a46889f9f340251bdf644f
Author: Srirangan Madhavan <smadhavan@nvidia.com>
cxl: Cache endpoint decoder settings during PCI enumeration
This patch populates pci_dev->hdm from PCI capability initialization
for CXL.mem functions. It temporarily sets memory space enable to read
HDM MMIO and restores the original configuration value.
> diff --git a/drivers/cxl/core/reset.c b/drivers/cxl/core/reset.c
> --- a/drivers/cxl/core/reset.c
> +++ b/drivers/cxl/core/reset.c
[ ... ]
> +static int __pci_cxl_hdm_init(struct pci_dev *pdev)
> +{
[ ... ]
> + if (!(command & PCI_COMMAND_MEMORY))
> + restore_command = true;
> +
> + if (restore_command) {
> + rc = pci_write_config_word(pdev, PCI_COMMAND,
> + command | PCI_COMMAND_MEMORY);
[Severity: High]
Is it safe to forcefully enable memory decoding before the PCI core has
verified or assigned safe base address registers?
Since this function is called during early enumeration in
pci_init_capabilities():
drivers/pci/probe.c:pci_init_capabilities() {
...
pci_ide_init(dev);
pci_cxl_hdm_init(dev);
...
}
Could uninitialized or overlapping physical addresses cause the endpoint to
decode transactions intended for system memory, leading to resource
conflicts or machine check exceptions?
> + if (rc)
> + return pcibios_err_to_errno(rc);
> + }
[ ... ]
> + scoped_guard(rwsem_write, &cxl_rwsem.dpa) {
> + if (pdev->hdm)
> + goto out_unmap;
[Severity: Medium]
Could this goto inside a scoped_guard() block lead to logical fall-through
bugs?
The cleanup subsystem guidelines advise against mixing goto and scope-based
cleanups in the same function. If pdev->hdm is already set, execution
jumps to out_unmap and then falls through to out_restore_command.
Could this cause the configuration write to be re-executed redundantly
during the error handling fall-through?
> + pdev->hdm = info;
> + }
> + iounmap(hdm);
> + return 0;
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260709010304.680422-1-smadhavan@nvidia.com?part=4
next prev parent reply other threads:[~2026-07-09 1:17 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-09 1:02 [PATCH v9 00/11] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-07-09 1:02 ` [PATCH v9 01/11] cxl: Split decoder programming into a reusable helper Srirangan Madhavan
2026-07-09 1:14 ` sashiko-bot
2026-07-09 1:02 ` [PATCH v9 02/11] cxl: Cache decoder settings on PCI devices Srirangan Madhavan
2026-07-09 1:16 ` sashiko-bot
2026-07-09 1:02 ` [PATCH v9 03/11] cxl: Share HDM decoder decode logic Srirangan Madhavan
2026-07-09 1:18 ` sashiko-bot
2026-07-09 1:02 ` [PATCH v9 04/11] cxl: Cache endpoint decoder settings during PCI enumeration Srirangan Madhavan
2026-07-09 1:17 ` sashiko-bot [this message]
2026-07-09 3:30 ` Alison Schofield
2026-07-10 0:48 ` Dan Williams (nvidia)
2026-07-09 1:02 ` [PATCH v9 05/11] cxl: Add CXL Device Reset helper Srirangan Madhavan
2026-07-09 1:15 ` sashiko-bot
2026-07-09 1:02 ` [PATCH v9 06/11] cxl: Validate HDM ranges before CXL reset Srirangan Madhavan
2026-07-09 1:28 ` sashiko-bot
2026-07-09 1:03 ` [PATCH v9 07/11] PCI/CXL: Discover the CXL reset scope Srirangan Madhavan
2026-07-09 1:24 ` sashiko-bot
2026-07-10 1:00 ` Dan Williams (nvidia)
2026-07-09 1:03 ` [PATCH v9 08/11] cxl: Restore CXL HDM state after PCI reset Srirangan Madhavan
2026-07-09 1:17 ` sashiko-bot
2026-07-09 1:03 ` [PATCH v9 09/11] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-07-09 1:27 ` sashiko-bot
2026-07-09 1:03 ` [PATCH v9 10/11] Documentation/ABI: Document CXL Reset " Srirangan Madhavan
2026-07-09 1:05 ` sashiko-bot
2026-07-09 1:03 ` [PATCH v9 11/11] PCI/CXL: Restore HDM state after CXL bus reset Srirangan Madhavan
2026-07-09 1:20 ` sashiko-bot
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