[bod:qcom-laptops-v6.18-rc4-camss-icp-bps-ipe-icp-boots+stats-b4 93/121] drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c:95:2-3: Unneeded semicolon

[kernel test robot <lkp@intel.com>]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/bod/linux.git qcom-laptops-v6.18-rc4-camss-icp-bps-ipe-icp-boots+stats-b4
head:   ebd1e440443121d18f730ab2aeea5586a754f36f
commit: d7952be2f35aa9609bdcb72055e2410f4754a056 [93/121] phy: qcom-mipi-csi2: Add a CSI2 MIPI DPHY driver
config: powerpc-randconfig-r052-20260708 (https://download.01.org/0day-ci/archive/20260709/202607092026.NvVOGEmF-lkp@intel.com/config)
compiler: clang version 23.0.0git (https://github.com/llvm/llvm-project c279890c85da307abe34f10333442bbf72a60644)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202607092026.NvVOGEmF-lkp@intel.com/

cocci warnings: (new ones prefixed by >>)
>> drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c:95:2-3: Unneeded semicolon

vim +95 drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c

    32	
    33	static int
    34	phy_qcom_mipi_csi2_set_clock_rates(struct mipi_csi2phy_device *csi2phy,
    35					   s64 link_freq)
    36	{
    37		const struct mipi_csi2phy_soc_cfg *soc_cfg = csi2phy->soc_cfg;
    38		unsigned long rates[MAX_CSI2PHY_CLKS] = {0};
    39		struct device *dev = csi2phy->dev;
    40		unsigned long max_opp_level;
    41		unsigned long vote_freq;
    42		struct dev_pm_opp *opp;
    43		int i, j;
    44		int ret;
    45	
    46		for (i = 0; i < soc_cfg->num_clk; i++) {
    47			const struct mipi_csi2phy_clk_freq *clk_freq = &soc_cfg->clk_freq[i];
    48			const char *clk_name = soc_cfg->clk_names[i];
    49			struct clk *clk = csi2phy->clks[i].clk;
    50			u64 min_rate = link_freq / 4;
    51			long round_rate;
    52	
    53			phy_qcom_mipi_csi2_add_clock_margin(&min_rate);
    54	
    55			/* This clock should be enabled only not set */
    56			if (!clk_freq->num_freq)
    57				continue;
    58	
    59			for (j = 0; j < clk_freq->num_freq; j++)
    60				if (min_rate < clk_freq->freq[j])
    61					break;
    62	
    63			if (j == clk_freq->num_freq) {
    64				dev_err(dev,
    65					"Pixel clock %llu is too high for %s\n",
    66					min_rate, clk_name);
    67				return -EINVAL;
    68			}
    69	
    70			/* if sensor pixel clock is not available
    71			 * set highest possible CSIPHY clock rate
    72			 */
    73			if (min_rate == 0)
    74				j = clk_freq->num_freq - 1;
    75	
    76			round_rate = clk_round_rate(clk, clk_freq->freq[j]);
    77			if (round_rate < 0) {
    78				dev_err(dev, "clk round rate failed: %ld\n",
    79					round_rate);
    80				return -EINVAL;
    81			}
    82	
    83			rates[i] = round_rate;
    84	
    85			if (!strcmp(clk_name, "csiphy_timer"))
    86				csi2phy->timer_clk_rate = round_rate;
    87	
    88			if (!strcmp(clk_name, "csiphy"))
    89				vote_freq = round_rate;
    90		}
    91	
    92		if (!vote_freq) {
    93			dev_err(dev, "Unable to find operating point frequency\n");
    94			return -ENODEV;
  > 95		};
    96	
    97		dev_dbg(dev, "OPP freq: %lu Hz\n", vote_freq);
    98	
    99		ret = dev_pm_opp_set_rate(dev, vote_freq);
   100		if (ret < 0) {
   101			dev_err(dev, "Failed to set OPP rate: %d\n", ret);
   102			return ret;
   103		}
   104	
   105		for (i = 0; i < soc_cfg->num_clk; i++) {
   106			if (rates[i] == 0)
   107				continue;
   108	
   109			dev_dbg(dev, "Setting clk %s to %lu Hz\n",
   110				soc_cfg->clk_names[i], rates[i]);
   111	
   112			ret = clk_set_rate(csi2phy->clks[i].clk, rates[i]);
   113			if (ret < 0) {
   114				dev_err(dev, "clk_set_rate failed for %s: %d\n",
   115					soc_cfg->clk_names[i], ret);
   116				return ret;
   117			}
   118		}
   119	
   120		return 0;
   121	}
   122	

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