From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AEA52157487; Fri, 10 Jul 2026 06:02:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783663330; cv=none; b=hE/LtCkKQFNSDcj9aWf4S0fE73HVuPWn3I4xU2Mpwh2LrVTR53jkohbIGjo7k4a4OT7atMOifErIVh7NY0hc6oFfI3OOeMzr480THLE/Zz0ME5gGov9I3kwtFPlLV4SOQIdNgyHGcRtHiaEwscRk9c7woANO+TD0gwzowDSEo8s= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783663330; c=relaxed/simple; bh=CPc0OmNLnBPIoGSrOd4ZGthnyLXyTsCPjh70df9LyJ0=; h=From:Subject:To:Cc:In-Reply-To:References:Content-Type:Date: Message-Id; b=iuoaTrKxDjy2sz/+sOEag3u4MoPFiygB4IOXvQhgoHolzpRyv3sp9Ax40MpvNMmwK8jbfuOBZE4f9Bx/TtWeGNnLZlkCX1o9cGcghQjLh7yt81NCQ10IF7YYit7eqrVkzeM1BiUSnV4/Qzyo9AdPn7GfF6T6Q3scOa8RNlc8gd8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gwW2LCD2; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gwW2LCD2" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E94341F000E9; Fri, 10 Jul 2026 06:02:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783663328; bh=ar0yGh+cIGAItWENq97rezTQTEq+OHxfFEYHf0XTmbU=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=gwW2LCD2guWUTPkDKuwnPHj3TaLiN8vnSvN/1+7VtkVjaB7SW4sxfp6ovmUPxpUdK tPs3f7Y+leQqddvCOJRqnwV6a5E4PbifVjFY8FY/a8H5dfAQeABZbNSPbBvzoRVe4U UUeNyLS4kNQIoVDGdaWVAF3DYBD0cy4U+dEMbZQZwg/2oankyA8BgmEox6BdsuIBxY aEoZoq2GoLDdKr2FZ7StkR9nAAGKDkCh4z33c4fuXqikEA9vUx0PV+kDq5APtymRHR RdqjBa03cGJE6Y9vmQLkb4EXDwKttijI1+d+m2d+8iqizIjtFTrCQWJ3sg+XEbYnHZ 4jQG481cIryZA== From: sashiko-bot@kernel.org Subject: Re: [PATCH v10 2/3] dmaengine: amlogic: Add general DMA driver for A9 Reply-To: sashiko-reviews@lists.linux.dev To: "Xianwei Zhao" Cc: Frank.Li@kernel.org, neil.armstrong@linaro.org, conor+dt@kernel.org, robh@kernel.org, vkoul@kernel.org, linux-amlogic@lists.infradead.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org In-Reply-To: <20260710-amlogic-dma-v10-2-ff4deae837e7@amlogic.com> References: <20260710-amlogic-dma-v10-0-ff4deae837e7@amlogic.com> <20260710-amlogic-dma-v10-2-ff4deae837e7@amlogic.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Fri, 10 Jul 2026 06:02:07 +0000 Message-Id: <20260710060207.E94341F000E9@smtp.kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Thank you for your contribution! Sashiko AI review found 9 potential issue(= s) to consider: - [High] Scheduled descriptor free works are never flushed, leading to a us= e-after-free on module unload. - [High] Missing IRQ synchronization before killing tasklets in remove() le= ads to use-after-free. - [High] Failure to check the return value of platform_get_irq() breaks def= erred probing. - [High] `SG_MAX_LEN` is defined as an unaligned maximum value, causing una= ligned physical address boundaries for subsequent DMA segments. - [High] Missing 64-bit DMA Mask Configuration forces SWIOTLB bounce buffer= ing on ARM64. - [High] Resuming a paused DMA channel fails to restart pending transfers, = leaving the channel permanently stalled. - [High] Missing src_addr_widths configuration breaks DEV_TO_MEM clients. - [Medium] Lockless status check leads to spurious errors and incorrect DMA= _IN_PROGRESS returns. - [Medium] aml_dma_tx_status() fails to report the DMA_PAUSED state. -- --- Patch [2]: [PATCH v10 2/3] dmaengine: amlogic: Add general DMA driver f= or A9 --- commit 99b90ddfd63851fd9f1a5c3ca30d4210c8de8c83 Author: Xianwei Zhao Subject: dmaengine: amlogic: Add general DMA driver for A9 This patch introduces a general-purpose DMA controller driver for Amlogic A9 SoCs. It includes support for virtual channels, SG list scatter/gather capabilities, and basic transfer modes like Mem-to-Dev and Dev-to-Mem. > diff --git a/drivers/dma/amlogic-dma.c b/drivers/dma/amlogic-dma.c > new file mode 100644 > index 0000000000000..388b5a581ae58 > --- /dev/null > +++ b/drivers/dma/amlogic-dma.c [ ... ] > +#define MAX_CHAN_ID 32 > +#define SG_MAX_LEN GENMASK(26, 0) [Severity: High] Does this define the segment boundary as an unaligned odd length? Since GENMASK(26, 0) equates to 134,217,727 bytes, which is an odd number, using it to split segments will corrupt the alignment of all subsequent physical addresses in the chain. Could this cause hardware alignment faults on the AXI bus for clients submitting large buffers? [ ... ] > +static enum dma_status aml_dma_tx_status(struct dma_chan *chan, > + dma_cookie_t cookie, > + struct dma_tx_state *txstate) > +{ > + struct aml_dma_chan *aml_chan =3D to_aml_dma_chan(chan); > + struct aml_dma_dev *aml_dma =3D aml_chan->aml_dma; > + struct aml_dma_desc *aml_desc =3D NULL; > + struct virt_dma_desc *vd; > + u32 residue =3D 0, done; > + unsigned long flags; > + enum dma_status ret; > + > + ret =3D dma_cookie_status(chan, cookie, txstate); > + if (ret =3D=3D DMA_COMPLETE || !txstate) > + return ret; [Severity: Medium] Should this function intercept the status to report DMA_PAUSED? The core dma_cookie_status() will return DMA_IN_PROGRESS for pending transfers. Because this unconditionally returns that value, it fails to substitute the driver's internal DMA_PAUSED state when the channel is paused. This prevents clients from detecting that a channel has successfully paused. > + > + spin_lock_irqsave(&aml_chan->vchan.lock, flags); > + vd =3D vchan_find_desc(&aml_chan->vchan, cookie); > + if (vd) { > + aml_desc =3D to_aml_dma_desc(vd); > + residue =3D aml_desc->data_len; > + } else if (aml_chan->cur_desc && aml_chan->cur_desc->vd.tx.cookie =3D= =3D cookie) { > + aml_desc =3D aml_chan->cur_desc; > + regmap_read(aml_dma->regmap, aml_chan->reg_offs + RCH_RD_LEN, &done); > + residue =3D aml_desc->data_len - done; > + } else { > + dev_err(aml_dma->dma_device.dev, "cookie error\n"); > + } [Severity: Medium] Can this lockless status check lead to spurious cookie errors? Since dma_cookie_status() is called before acquiring the lock, the transfer could complete immediately after the check. By the time the lock is acquired, vchan_find_desc() will fail to find the descriptor, falling through to the else branch. This would print a spurious "cookie error" and return a stale DMA_IN_PROGRESS status with a zero residue. Would re-evaluating the cookie status inside the lock prevent this race? [ ... ] > + sg_link =3D aml_desc->sg_link; > + for_each_sg(sgl, sg, sg_len, i) { > + avail =3D sg_dma_len(sg); > + if (avail =3D=3D 0) > + continue; > + paddr =3D sg->dma_address; > + while (avail > SG_MAX_LEN) { > + /* set dma address and len to sglink*/ > + sg_link->addr_low =3D lower_32_bits(paddr); > + sg_link->addr_high =3D upper_32_bits(paddr); > + sg_link->ctl =3D FIELD_PREP(LINK_LEN, SG_MAX_LEN); > + paddr =3D paddr + SG_MAX_LEN; > + avail =3D avail - SG_MAX_LEN; > + sg_link++; > + } [Severity: High] Will this split corrupt the physical address alignment? Because SG_MAX_LEN is an odd number, adding it to paddr guarantees that the subsequent segment will start at an unaligned physical address. Could this cause hardware faults during transfers? [ ... ] > +static int aml_dma_chan_resume(struct dma_chan *chan) > +{ > + struct aml_dma_chan *aml_chan =3D to_aml_dma_chan(chan); > + struct aml_dma_dev *aml_dma =3D aml_chan->aml_dma; > + unsigned long flags; > + > + spin_lock_irqsave(&aml_chan->vchan.lock, flags); > + regmap_clear_bits(aml_dma->regmap, aml_chan->reg_offs + RCH_CFG, CFG_PA= USE); > + aml_chan->status =3D aml_chan->pre_status; > + spin_unlock_irqrestore(&aml_chan->vchan.lock, flags); > + > + return 0; > +} [Severity: High] Does this function need to inspect the desc_issued list or call aml_dma_start() after clearing the pause state? If a client queues a new transfer and calls issue_pending() while the channel is paused, aml_dma_start() returns early. The transfer stays in desc_issued. Without a call to aml_dma_start() during resume, the queued descriptors remain trapped indefinitely and the channel stalls. [ ... ] > +static int aml_dma_probe(struct platform_device *pdev) > +{ > + struct device_node *np =3D pdev->dev.of_node; > + struct dma_device *dma_dev; > + struct aml_dma_dev *aml_dma; > + int ret, i, len; > + u32 chan_nr; [ ... ] > + aml_dma->clk =3D devm_clk_get_enabled(&pdev->dev, NULL); > + if (IS_ERR(aml_dma->clk)) > + return PTR_ERR(aml_dma->clk); > + > + aml_dma->irq =3D platform_get_irq(pdev, 0); > + > + aml_dma->pdev =3D pdev; > + aml_dma->dma_device.dev =3D &pdev->dev; [Severity: High] Can this break deferred probing if platform_get_irq() fails? If platform_get_irq() returns -EPROBE_DEFER, storing it directly without checking for negative errors means it will later be passed to devm_request_irq(). The request will treat it as a massive invalid IRQ number and reject it with -EINVAL, permanently failing the probe. [Severity: High] Does the DMA device initialization here miss declaring 64-bit addressing capabilities to the core framework? The hardware naturally supports 64-bit physical addresses, but since dma_set_mask_and_coherent() is never called to set a 64-bit mask, the framework will fall back to a 32-bit mask. Will this force any memory mapped above 4GB to use SWIOTLB bounce buffers on ARM64 systems? [ ... ] > + dma_set_max_seg_size(dma_dev->dev, SG_MAX_LEN); > + dma_cap_set(DMA_SLAVE, dma_dev->cap_mask); > + dma_dev->device_alloc_chan_resources =3D aml_dma_alloc_chan_resources; > + dma_dev->device_free_chan_resources =3D aml_dma_free_chan_resources; > + dma_dev->device_tx_status =3D aml_dma_tx_status; > + dma_dev->device_prep_slave_sg =3D aml_dma_prep_slave_sg; > + dma_dev->device_pause =3D aml_dma_chan_pause; > + dma_dev->device_resume =3D aml_dma_chan_resume; > + dma_dev->device_terminate_all =3D aml_dma_terminate_all; > + dma_dev->device_issue_pending =3D aml_dma_issue_pending; > + /* PIO 4 bytes and I2C 1 byte */ > + dma_dev->dst_addr_widths =3D BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_= SLAVE_BUSWIDTH_1_BYTE); > + dma_dev->directions =3D BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); > + dma_dev->residue_granularity =3D DMA_RESIDUE_GRANULARITY_BURST; [Severity: High] Does missing src_addr_widths configuration break DEV_TO_MEM clients? The driver advertises DMA_DEV_TO_MEM support, but only populates dst_addr_widths. When generic DMA clients (like ALSA/ASoC) attempt to configure the channel for capture (Rx), the capability check will fail because src_addr_widths is 0, causing the framework to reject the channel. [ ... ] > +static void aml_dma_remove(struct platform_device *pdev) > +{ > + struct aml_dma_dev *aml_dma =3D platform_get_drvdata(pdev); > + struct aml_dma_chan *aml_chan =3D NULL; > + int i; > + > + of_dma_controller_free((&pdev->dev)->of_node); > + > + regmap_write(aml_dma->regmap, RCH_INT_MASK, 0xffffffff); > + regmap_write(aml_dma->regmap, WCH_INT_MASK, 0xffffffff); [Severity: High] Could unloading this module lead to a use-after-free from un-flushed work? The aml_dma_free_desc() function schedules free_work on the global system workqueue. If a DMA channel is freed just before or during module unload, the scheduled work is not flushed or waited upon before devres drops the backing memory. The asynchronous work will execute after aml_dma is freed, dereferencing a dangling pointer. > + > + for (i =3D 0; i < MAX_CHAN_ID; i++) { > + aml_chan =3D aml_dma->aml_rch[i]; > + if (aml_chan) > + tasklet_kill(&aml_chan->vchan.task); > + aml_chan =3D aml_dma->aml_wch[i]; > + if (aml_chan) > + tasklet_kill(&aml_chan->vchan.task); > + } > +} [Severity: High] Does killing tasklets here without IRQ synchronization expose a race window? Because devm_request_irq() is used, the interrupt is freed by devres after remove() completes. If an interrupt handler is actively executing on another CPU, it can call tasklet_schedule() immediately after tasklet_kill() finishes. Devres then frees the structures, and the newly scheduled tasklet will later execute on freed memory in the softirq context. Would calling synchronize_irq() before killing tasklets prevent this? --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20260710-amlogic-dm= a-v10-0-ff4deae837e7@amlogic.com?part=3D2 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7C39BC43458 for ; Fri, 10 Jul 2026 06:02:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Reply-To:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: References:In-Reply-To:Cc:To:Subject:From:Content-ID:Content-Description: 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sea.source.kernel.org (Postfix) with ESMTP id 8197940168; Fri, 10 Jul 2026 06:02:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E94341F000E9; Fri, 10 Jul 2026 06:02:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783663328; bh=ar0yGh+cIGAItWENq97rezTQTEq+OHxfFEYHf0XTmbU=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=gwW2LCD2guWUTPkDKuwnPHj3TaLiN8vnSvN/1+7VtkVjaB7SW4sxfp6ovmUPxpUdK tPs3f7Y+leQqddvCOJRqnwV6a5E4PbifVjFY8FY/a8H5dfAQeABZbNSPbBvzoRVe4U UUeNyLS4kNQIoVDGdaWVAF3DYBD0cy4U+dEMbZQZwg/2oankyA8BgmEox6BdsuIBxY aEoZoq2GoLDdKr2FZ7StkR9nAAGKDkCh4z33c4fuXqikEA9vUx0PV+kDq5APtymRHR RdqjBa03cGJE6Y9vmQLkb4EXDwKttijI1+d+m2d+8iqizIjtFTrCQWJ3sg+XEbYnHZ 4jQG481cIryZA== From: sashiko-bot@kernel.org Subject: Re: [PATCH v10 2/3] dmaengine: amlogic: Add general DMA driver for A9 To: "Xianwei Zhao" Cc: Frank.Li@kernel.org, neil.armstrong@linaro.org, conor+dt@kernel.org, robh@kernel.org, vkoul@kernel.org, linux-amlogic@lists.infradead.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org In-Reply-To: <20260710-amlogic-dma-v10-2-ff4deae837e7@amlogic.com> References: <20260710-amlogic-dma-v10-0-ff4deae837e7@amlogic.com> <20260710-amlogic-dma-v10-2-ff4deae837e7@amlogic.com> Date: Fri, 10 Jul 2026 06:02:07 +0000 Message-Id: <20260710060207.E94341F000E9@smtp.kernel.org> X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: sashiko-reviews@lists.linux.dev MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org VGhhbmsgeW91IGZvciB5b3VyIGNvbnRyaWJ1dGlvbiEgU2FzaGlrbyBBSSByZXZpZXcgZm91bmQg OSBwb3RlbnRpYWwgaXNzdWUocykgdG8gY29uc2lkZXI6Ci0gW0hpZ2hdIFNjaGVkdWxlZCBkZXNj cmlwdG9yIGZyZWUgd29ya3MgYXJlIG5ldmVyIGZsdXNoZWQsIGxlYWRpbmcgdG8gYSB1c2UtYWZ0 ZXItZnJlZSBvbiBtb2R1bGUgdW5sb2FkLgotIFtIaWdoXSBNaXNzaW5nIElSUSBzeW5jaHJvbml6 YXRpb24gYmVmb3JlIGtpbGxpbmcgdGFza2xldHMgaW4gcmVtb3ZlKCkgbGVhZHMgdG8gdXNlLWFm dGVyLWZyZWUuCi0gW0hpZ2hdIEZhaWx1cmUgdG8gY2hlY2sgdGhlIHJldHVybiB2YWx1ZSBvZiBw bGF0Zm9ybV9nZXRfaXJxKCkgYnJlYWtzIGRlZmVycmVkIHByb2JpbmcuCi0gW0hpZ2hdIGBTR19N QVhfTEVOYCBpcyBkZWZpbmVkIGFzIGFuIHVuYWxpZ25lZCBtYXhpbXVtIHZhbHVlLCBjYXVzaW5n IHVuYWxpZ25lZCBwaHlzaWNhbCBhZGRyZXNzIGJvdW5kYXJpZXMgZm9yIHN1YnNlcXVlbnQgRE1B IHNlZ21lbnRzLgotIFtIaWdoXSBNaXNzaW5nIDY0LWJpdCBETUEgTWFzayBDb25maWd1cmF0aW9u IGZvcmNlcyBTV0lPVExCIGJvdW5jZSBidWZmZXJpbmcgb24gQVJNNjQuCi0gW0hpZ2hdIFJlc3Vt aW5nIGEgcGF1c2VkIERNQSBjaGFubmVsIGZhaWxzIHRvIHJlc3RhcnQgcGVuZGluZyB0cmFuc2Zl cnMsIGxlYXZpbmcgdGhlIGNoYW5uZWwgcGVybWFuZW50bHkgc3RhbGxlZC4KLSBbSGlnaF0gTWlz c2luZyBzcmNfYWRkcl93aWR0aHMgY29uZmlndXJhdGlvbiBicmVha3MgREVWX1RPX01FTSBjbGll bnRzLgotIFtNZWRpdW1dIExvY2tsZXNzIHN0YXR1cyBjaGVjayBsZWFkcyB0byBzcHVyaW91cyBl cnJvcnMgYW5kIGluY29ycmVjdCBETUFfSU5fUFJPR1JFU1MgcmV0dXJucy4KLSBbTWVkaXVtXSBh bWxfZG1hX3R4X3N0YXR1cygpIGZhaWxzIHRvIHJlcG9ydCB0aGUgRE1BX1BBVVNFRCBzdGF0ZS4K LS0KCi0tLSBQYXRjaCBbMl06IFtQQVRDSCB2MTAgMi8zXSBkbWFlbmdpbmU6IGFtbG9naWM6IEFk ZCBnZW5lcmFsIERNQSBkcml2ZXIgZm9yIEE5IC0tLQpjb21taXQgOTliOTBkZGZkNjM4NTFmZDlm MWE1YzNjYTMwZDQyMTBjOGRlOGM4MwpBdXRob3I6IFhpYW53ZWkgWmhhbyA8eGlhbndlaS56aGFv QGFtbG9naWMuY29tPgpTdWJqZWN0OiBkbWFlbmdpbmU6IGFtbG9naWM6IEFkZCBnZW5lcmFsIERN QSBkcml2ZXIgZm9yIEE5CgpUaGlzIHBhdGNoIGludHJvZHVjZXMgYSBnZW5lcmFsLXB1cnBvc2Ug RE1BIGNvbnRyb2xsZXIgZHJpdmVyIGZvciBBbWxvZ2ljCkE5IFNvQ3MuIEl0IGluY2x1ZGVzIHN1 cHBvcnQgZm9yIHZpcnR1YWwgY2hhbm5lbHMsIFNHIGxpc3Qgc2NhdHRlci9nYXRoZXIKY2FwYWJp bGl0aWVzLCBhbmQgYmFzaWMgdHJhbnNmZXIgbW9kZXMgbGlrZSBNZW0tdG8tRGV2IGFuZCBEZXYt dG8tTWVtLgoKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9kbWEvYW1sb2dpYy1kbWEuYyBiL2RyaXZl cnMvZG1hL2FtbG9naWMtZG1hLmMKPiBuZXcgZmlsZSBtb2RlIDEwMDY0NAo+IGluZGV4IDAwMDAw MDAwMDAwMDAuLjM4OGI1YTU4MWFlNTgKPiAtLS0gL2Rldi9udWxsCj4gKysrIGIvZHJpdmVycy9k bWEvYW1sb2dpYy1kbWEuYwoKWyAuLi4gXQoKPiArI2RlZmluZSBNQVhfQ0hBTl9JRAkJMzIKPiAr I2RlZmluZSBTR19NQVhfTEVOCQlHRU5NQVNLKDI2LCAwKQoKW1NldmVyaXR5OiBIaWdoXQpEb2Vz IHRoaXMgZGVmaW5lIHRoZSBzZWdtZW50IGJvdW5kYXJ5IGFzIGFuIHVuYWxpZ25lZCBvZGQgbGVu Z3RoPwoKU2luY2UgR0VOTUFTSygyNiwgMCkgZXF1YXRlcyB0byAxMzQsMjE3LDcyNyBieXRlcywg d2hpY2ggaXMgYW4gb2RkIG51bWJlciwKdXNpbmcgaXQgdG8gc3BsaXQgc2VnbWVudHMgd2lsbCBj b3JydXB0IHRoZSBhbGlnbm1lbnQgb2YgYWxsIHN1YnNlcXVlbnQKcGh5c2ljYWwgYWRkcmVzc2Vz IGluIHRoZSBjaGFpbi4KCkNvdWxkIHRoaXMgY2F1c2UgaGFyZHdhcmUgYWxpZ25tZW50IGZhdWx0 cyBvbiB0aGUgQVhJIGJ1cyBmb3IgY2xpZW50cwpzdWJtaXR0aW5nIGxhcmdlIGJ1ZmZlcnM/Cgpb IC4uLiBdCgo+ICtzdGF0aWMgZW51bSBkbWFfc3RhdHVzIGFtbF9kbWFfdHhfc3RhdHVzKHN0cnVj dCBkbWFfY2hhbiAqY2hhbiwKPiArCQkJCQkgZG1hX2Nvb2tpZV90IGNvb2tpZSwKPiArCQkJCQkg c3RydWN0IGRtYV90eF9zdGF0ZSAqdHhzdGF0ZSkKPiArewo+ICsJc3RydWN0IGFtbF9kbWFfY2hh biAqYW1sX2NoYW4gPSB0b19hbWxfZG1hX2NoYW4oY2hhbik7Cj4gKwlzdHJ1Y3QgYW1sX2RtYV9k ZXYgKmFtbF9kbWEgPSBhbWxfY2hhbi0+YW1sX2RtYTsKPiArCXN0cnVjdCBhbWxfZG1hX2Rlc2Mg KmFtbF9kZXNjID0gTlVMTDsKPiArCXN0cnVjdCB2aXJ0X2RtYV9kZXNjICp2ZDsKPiArCXUzMiBy ZXNpZHVlID0gMCwgZG9uZTsKPiArCXVuc2lnbmVkIGxvbmcgZmxhZ3M7Cj4gKwllbnVtIGRtYV9z dGF0dXMgcmV0Owo+ICsKPiArCXJldCA9IGRtYV9jb29raWVfc3RhdHVzKGNoYW4sIGNvb2tpZSwg dHhzdGF0ZSk7Cj4gKwlpZiAocmV0ID09IERNQV9DT01QTEVURSB8fCAhdHhzdGF0ZSkKPiArCQly ZXR1cm4gcmV0OwoKW1NldmVyaXR5OiBNZWRpdW1dClNob3VsZCB0aGlzIGZ1bmN0aW9uIGludGVy Y2VwdCB0aGUgc3RhdHVzIHRvIHJlcG9ydCBETUFfUEFVU0VEPwoKVGhlIGNvcmUgZG1hX2Nvb2tp ZV9zdGF0dXMoKSB3aWxsIHJldHVybiBETUFfSU5fUFJPR1JFU1MgZm9yIHBlbmRpbmcKdHJhbnNm ZXJzLiBCZWNhdXNlIHRoaXMgdW5jb25kaXRpb25hbGx5IHJldHVybnMgdGhhdCB2YWx1ZSwgaXQg ZmFpbHMgdG8Kc3Vic3RpdHV0ZSB0aGUgZHJpdmVyJ3MgaW50ZXJuYWwgRE1BX1BBVVNFRCBzdGF0 ZSB3aGVuIHRoZSBjaGFubmVsIGlzCnBhdXNlZC4KClRoaXMgcHJldmVudHMgY2xpZW50cyBmcm9t IGRldGVjdGluZyB0aGF0IGEgY2hhbm5lbCBoYXMgc3VjY2Vzc2Z1bGx5IHBhdXNlZC4KCj4gKwo+ ICsJc3Bpbl9sb2NrX2lycXNhdmUoJmFtbF9jaGFuLT52Y2hhbi5sb2NrLCBmbGFncyk7Cj4gKwl2 ZCA9IHZjaGFuX2ZpbmRfZGVzYygmYW1sX2NoYW4tPnZjaGFuLCBjb29raWUpOwo+ICsJaWYgKHZk KSB7Cj4gKwkJYW1sX2Rlc2MgPSB0b19hbWxfZG1hX2Rlc2ModmQpOwo+ICsJCXJlc2lkdWUgPSBh bWxfZGVzYy0+ZGF0YV9sZW47Cj4gKwl9IGVsc2UgaWYgKGFtbF9jaGFuLT5jdXJfZGVzYyAmJiBh bWxfY2hhbi0+Y3VyX2Rlc2MtPnZkLnR4LmNvb2tpZSA9PSBjb29raWUpIHsKPiArCQlhbWxfZGVz YyA9IGFtbF9jaGFuLT5jdXJfZGVzYzsKPiArCQlyZWdtYXBfcmVhZChhbWxfZG1hLT5yZWdtYXAs IGFtbF9jaGFuLT5yZWdfb2ZmcyArIFJDSF9SRF9MRU4sICZkb25lKTsKPiArCQlyZXNpZHVlID0g YW1sX2Rlc2MtPmRhdGFfbGVuIC0gZG9uZTsKPiArCX0gZWxzZSB7Cj4gKwkJZGV2X2VycihhbWxf ZG1hLT5kbWFfZGV2aWNlLmRldiwgImNvb2tpZSBlcnJvclxuIik7Cj4gKwl9CgpbU2V2ZXJpdHk6 IE1lZGl1bV0KQ2FuIHRoaXMgbG9ja2xlc3Mgc3RhdHVzIGNoZWNrIGxlYWQgdG8gc3B1cmlvdXMg Y29va2llIGVycm9ycz8KClNpbmNlIGRtYV9jb29raWVfc3RhdHVzKCkgaXMgY2FsbGVkIGJlZm9y ZSBhY3F1aXJpbmcgdGhlIGxvY2ssIHRoZSB0cmFuc2Zlcgpjb3VsZCBjb21wbGV0ZSBpbW1lZGlh dGVseSBhZnRlciB0aGUgY2hlY2suIEJ5IHRoZSB0aW1lIHRoZSBsb2NrIGlzCmFjcXVpcmVkLCB2 Y2hhbl9maW5kX2Rlc2MoKSB3aWxsIGZhaWwgdG8gZmluZCB0aGUgZGVzY3JpcHRvciwgZmFsbGlu Zwp0aHJvdWdoIHRvIHRoZSBlbHNlIGJyYW5jaC4KClRoaXMgd291bGQgcHJpbnQgYSBzcHVyaW91 cyAiY29va2llIGVycm9yIiBhbmQgcmV0dXJuIGEgc3RhbGUKRE1BX0lOX1BST0dSRVNTIHN0YXR1 cyB3aXRoIGEgemVybyByZXNpZHVlLiBXb3VsZCByZS1ldmFsdWF0aW5nIHRoZSBjb29raWUKc3Rh dHVzIGluc2lkZSB0aGUgbG9jayBwcmV2ZW50IHRoaXMgcmFjZT8KClsgLi4uIF0KCj4gKwlzZ19s aW5rID0gYW1sX2Rlc2MtPnNnX2xpbms7Cj4gKwlmb3JfZWFjaF9zZyhzZ2wsIHNnLCBzZ19sZW4s IGkpIHsKPiArCQlhdmFpbCA9IHNnX2RtYV9sZW4oc2cpOwo+ICsJCWlmIChhdmFpbCA9PSAwKQo+ ICsJCQljb250aW51ZTsKPiArCQlwYWRkciA9IHNnLT5kbWFfYWRkcmVzczsKPiArCQl3aGlsZSAo YXZhaWwgPiBTR19NQVhfTEVOKSB7Cj4gKwkJCS8qIHNldCBkbWEgYWRkcmVzcyBhbmQgbGVuIHRv IHNnbGluayovCj4gKwkJCXNnX2xpbmstPmFkZHJfbG93ID0gbG93ZXJfMzJfYml0cyhwYWRkcik7 Cj4gKwkJCXNnX2xpbmstPmFkZHJfaGlnaCA9IHVwcGVyXzMyX2JpdHMocGFkZHIpOwo+ICsJCQlz Z19saW5rLT5jdGwgPSBGSUVMRF9QUkVQKExJTktfTEVOLCBTR19NQVhfTEVOKTsKPiArCQkJcGFk ZHIgPSBwYWRkciArIFNHX01BWF9MRU47Cj4gKwkJCWF2YWlsID0gYXZhaWwgLSBTR19NQVhfTEVO Owo+ICsJCQlzZ19saW5rKys7Cj4gKwkJfQoKW1NldmVyaXR5OiBIaWdoXQpXaWxsIHRoaXMgc3Bs aXQgY29ycnVwdCB0aGUgcGh5c2ljYWwgYWRkcmVzcyBhbGlnbm1lbnQ/CgpCZWNhdXNlIFNHX01B WF9MRU4gaXMgYW4gb2RkIG51bWJlciwgYWRkaW5nIGl0IHRvIHBhZGRyIGd1YXJhbnRlZXMgdGhh dCB0aGUKc3Vic2VxdWVudCBzZWdtZW50IHdpbGwgc3RhcnQgYXQgYW4gdW5hbGlnbmVkIHBoeXNp Y2FsIGFkZHJlc3MuIENvdWxkIHRoaXMKY2F1c2UgaGFyZHdhcmUgZmF1bHRzIGR1cmluZyB0cmFu c2ZlcnM/CgpbIC4uLiBdCgo+ICtzdGF0aWMgaW50IGFtbF9kbWFfY2hhbl9yZXN1bWUoc3RydWN0 IGRtYV9jaGFuICpjaGFuKQo+ICt7Cj4gKwlzdHJ1Y3QgYW1sX2RtYV9jaGFuICphbWxfY2hhbiA9 IHRvX2FtbF9kbWFfY2hhbihjaGFuKTsKPiArCXN0cnVjdCBhbWxfZG1hX2RldiAqYW1sX2RtYSA9 IGFtbF9jaGFuLT5hbWxfZG1hOwo+ICsJdW5zaWduZWQgbG9uZyBmbGFnczsKPiArCj4gKwlzcGlu X2xvY2tfaXJxc2F2ZSgmYW1sX2NoYW4tPnZjaGFuLmxvY2ssIGZsYWdzKTsKPiArCXJlZ21hcF9j bGVhcl9iaXRzKGFtbF9kbWEtPnJlZ21hcCwgYW1sX2NoYW4tPnJlZ19vZmZzICsgUkNIX0NGRywg Q0ZHX1BBVVNFKTsKPiArCWFtbF9jaGFuLT5zdGF0dXMgPSBhbWxfY2hhbi0+cHJlX3N0YXR1czsK PiArCXNwaW5fdW5sb2NrX2lycXJlc3RvcmUoJmFtbF9jaGFuLT52Y2hhbi5sb2NrLCBmbGFncyk7 Cj4gKwo+ICsJcmV0dXJuIDA7Cj4gK30KCltTZXZlcml0eTogSGlnaF0KRG9lcyB0aGlzIGZ1bmN0 aW9uIG5lZWQgdG8gaW5zcGVjdCB0aGUgZGVzY19pc3N1ZWQgbGlzdCBvciBjYWxsCmFtbF9kbWFf c3RhcnQoKSBhZnRlciBjbGVhcmluZyB0aGUgcGF1c2Ugc3RhdGU/CgpJZiBhIGNsaWVudCBxdWV1 ZXMgYSBuZXcgdHJhbnNmZXIgYW5kIGNhbGxzIGlzc3VlX3BlbmRpbmcoKSB3aGlsZSB0aGUKY2hh bm5lbCBpcyBwYXVzZWQsIGFtbF9kbWFfc3RhcnQoKSByZXR1cm5zIGVhcmx5LiBUaGUgdHJhbnNm ZXIgc3RheXMgaW4KZGVzY19pc3N1ZWQuCgpXaXRob3V0IGEgY2FsbCB0byBhbWxfZG1hX3N0YXJ0 KCkgZHVyaW5nIHJlc3VtZSwgdGhlIHF1ZXVlZCBkZXNjcmlwdG9ycwpyZW1haW4gdHJhcHBlZCBp bmRlZmluaXRlbHkgYW5kIHRoZSBjaGFubmVsIHN0YWxscy4KClsgLi4uIF0KCj4gK3N0YXRpYyBp bnQgYW1sX2RtYV9wcm9iZShzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2KQo+ICt7Cj4gKwlz dHJ1Y3QgZGV2aWNlX25vZGUgKm5wID0gcGRldi0+ZGV2Lm9mX25vZGU7Cj4gKwlzdHJ1Y3QgZG1h X2RldmljZSAqZG1hX2RldjsKPiArCXN0cnVjdCBhbWxfZG1hX2RldiAqYW1sX2RtYTsKPiArCWlu dCByZXQsIGksIGxlbjsKPiArCXUzMiBjaGFuX25yOwoKWyAuLi4gXQoKPiArCWFtbF9kbWEtPmNs ayA9IGRldm1fY2xrX2dldF9lbmFibGVkKCZwZGV2LT5kZXYsIE5VTEwpOwo+ICsJaWYgKElTX0VS UihhbWxfZG1hLT5jbGspKQo+ICsJCXJldHVybiBQVFJfRVJSKGFtbF9kbWEtPmNsayk7Cj4gKwo+ ICsJYW1sX2RtYS0+aXJxID0gcGxhdGZvcm1fZ2V0X2lycShwZGV2LCAwKTsKPiArCj4gKwlhbWxf ZG1hLT5wZGV2ID0gcGRldjsKPiArCWFtbF9kbWEtPmRtYV9kZXZpY2UuZGV2ID0gJnBkZXYtPmRl djsKCltTZXZlcml0eTogSGlnaF0KQ2FuIHRoaXMgYnJlYWsgZGVmZXJyZWQgcHJvYmluZyBpZiBw bGF0Zm9ybV9nZXRfaXJxKCkgZmFpbHM/CgpJZiBwbGF0Zm9ybV9nZXRfaXJxKCkgcmV0dXJucyAt RVBST0JFX0RFRkVSLCBzdG9yaW5nIGl0IGRpcmVjdGx5IHdpdGhvdXQKY2hlY2tpbmcgZm9yIG5l Z2F0aXZlIGVycm9ycyBtZWFucyBpdCB3aWxsIGxhdGVyIGJlIHBhc3NlZCB0bwpkZXZtX3JlcXVl c3RfaXJxKCkuCgpUaGUgcmVxdWVzdCB3aWxsIHRyZWF0IGl0IGFzIGEgbWFzc2l2ZSBpbnZhbGlk IElSUSBudW1iZXIgYW5kIHJlamVjdCBpdAp3aXRoIC1FSU5WQUwsIHBlcm1hbmVudGx5IGZhaWxp bmcgdGhlIHByb2JlLgoKW1NldmVyaXR5OiBIaWdoXQpEb2VzIHRoZSBETUEgZGV2aWNlIGluaXRp YWxpemF0aW9uIGhlcmUgbWlzcyBkZWNsYXJpbmcgNjQtYml0IGFkZHJlc3NpbmcKY2FwYWJpbGl0 aWVzIHRvIHRoZSBjb3JlIGZyYW1ld29yaz8KClRoZSBoYXJkd2FyZSBuYXR1cmFsbHkgc3VwcG9y dHMgNjQtYml0IHBoeXNpY2FsIGFkZHJlc3NlcywgYnV0IHNpbmNlCmRtYV9zZXRfbWFza19hbmRf Y29oZXJlbnQoKSBpcyBuZXZlciBjYWxsZWQgdG8gc2V0IGEgNjQtYml0IG1hc2ssIHRoZQpmcmFt ZXdvcmsgd2lsbCBmYWxsIGJhY2sgdG8gYSAzMi1iaXQgbWFzay4KCldpbGwgdGhpcyBmb3JjZSBh bnkgbWVtb3J5IG1hcHBlZCBhYm92ZSA0R0IgdG8gdXNlIFNXSU9UTEIgYm91bmNlIGJ1ZmZlcnMK b24gQVJNNjQgc3lzdGVtcz8KClsgLi4uIF0KCj4gKwlkbWFfc2V0X21heF9zZWdfc2l6ZShkbWFf ZGV2LT5kZXYsIFNHX01BWF9MRU4pOwo+ICsJZG1hX2NhcF9zZXQoRE1BX1NMQVZFLCBkbWFfZGV2 LT5jYXBfbWFzayk7Cj4gKwlkbWFfZGV2LT5kZXZpY2VfYWxsb2NfY2hhbl9yZXNvdXJjZXMgPSBh bWxfZG1hX2FsbG9jX2NoYW5fcmVzb3VyY2VzOwo+ICsJZG1hX2Rldi0+ZGV2aWNlX2ZyZWVfY2hh bl9yZXNvdXJjZXMgPSBhbWxfZG1hX2ZyZWVfY2hhbl9yZXNvdXJjZXM7Cj4gKwlkbWFfZGV2LT5k ZXZpY2VfdHhfc3RhdHVzID0gYW1sX2RtYV90eF9zdGF0dXM7Cj4gKwlkbWFfZGV2LT5kZXZpY2Vf cHJlcF9zbGF2ZV9zZyA9IGFtbF9kbWFfcHJlcF9zbGF2ZV9zZzsKPiArCWRtYV9kZXYtPmRldmlj ZV9wYXVzZSA9IGFtbF9kbWFfY2hhbl9wYXVzZTsKPiArCWRtYV9kZXYtPmRldmljZV9yZXN1bWUg PSBhbWxfZG1hX2NoYW5fcmVzdW1lOwo+ICsJZG1hX2Rldi0+ZGV2aWNlX3Rlcm1pbmF0ZV9hbGwg PSBhbWxfZG1hX3Rlcm1pbmF0ZV9hbGw7Cj4gKwlkbWFfZGV2LT5kZXZpY2VfaXNzdWVfcGVuZGlu ZyA9IGFtbF9kbWFfaXNzdWVfcGVuZGluZzsKPiArCS8qIFBJTyA0IGJ5dGVzIGFuZCBJMkMgMSBi eXRlICovCj4gKwlkbWFfZGV2LT5kc3RfYWRkcl93aWR0aHMgPSBCSVQoRE1BX1NMQVZFX0JVU1dJ RFRIXzRfQllURVMpIHwgQklUKERNQV9TTEFWRV9CVVNXSURUSF8xX0JZVEUpOwo+ICsJZG1hX2Rl di0+ZGlyZWN0aW9ucyA9IEJJVChETUFfREVWX1RPX01FTSkgfCBCSVQoRE1BX01FTV9UT19ERVYp Owo+ICsJZG1hX2Rldi0+cmVzaWR1ZV9ncmFudWxhcml0eSA9IERNQV9SRVNJRFVFX0dSQU5VTEFS SVRZX0JVUlNUOwoKW1NldmVyaXR5OiBIaWdoXQpEb2VzIG1pc3Npbmcgc3JjX2FkZHJfd2lkdGhz IGNvbmZpZ3VyYXRpb24gYnJlYWsgREVWX1RPX01FTSBjbGllbnRzPwoKVGhlIGRyaXZlciBhZHZl cnRpc2VzIERNQV9ERVZfVE9fTUVNIHN1cHBvcnQsIGJ1dCBvbmx5IHBvcHVsYXRlcwpkc3RfYWRk cl93aWR0aHMuCgpXaGVuIGdlbmVyaWMgRE1BIGNsaWVudHMgKGxpa2UgQUxTQS9BU29DKSBhdHRl bXB0IHRvIGNvbmZpZ3VyZSB0aGUgY2hhbm5lbApmb3IgY2FwdHVyZSAoUngpLCB0aGUgY2FwYWJp bGl0eSBjaGVjayB3aWxsIGZhaWwgYmVjYXVzZSBzcmNfYWRkcl93aWR0aHMKaXMgMCwgY2F1c2lu ZyB0aGUgZnJhbWV3b3JrIHRvIHJlamVjdCB0aGUgY2hhbm5lbC4KClsgLi4uIF0KCj4gK3N0YXRp YyB2b2lkIGFtbF9kbWFfcmVtb3ZlKHN0cnVjdCBwbGF0Zm9ybV9kZXZpY2UgKnBkZXYpCj4gK3sK PiArCXN0cnVjdCBhbWxfZG1hX2RldiAqYW1sX2RtYSA9IHBsYXRmb3JtX2dldF9kcnZkYXRhKHBk ZXYpOwo+ICsJc3RydWN0IGFtbF9kbWFfY2hhbiAqYW1sX2NoYW4gPSBOVUxMOwo+ICsJaW50IGk7 Cj4gKwo+ICsJb2ZfZG1hX2NvbnRyb2xsZXJfZnJlZSgoJnBkZXYtPmRldiktPm9mX25vZGUpOwo+ ICsKPiArCXJlZ21hcF93cml0ZShhbWxfZG1hLT5yZWdtYXAsIFJDSF9JTlRfTUFTSywgMHhmZmZm ZmZmZik7Cj4gKwlyZWdtYXBfd3JpdGUoYW1sX2RtYS0+cmVnbWFwLCBXQ0hfSU5UX01BU0ssIDB4 ZmZmZmZmZmYpOwoKW1NldmVyaXR5OiBIaWdoXQpDb3VsZCB1bmxvYWRpbmcgdGhpcyBtb2R1bGUg bGVhZCB0byBhIHVzZS1hZnRlci1mcmVlIGZyb20gdW4tZmx1c2hlZCB3b3JrPwoKVGhlIGFtbF9k bWFfZnJlZV9kZXNjKCkgZnVuY3Rpb24gc2NoZWR1bGVzIGZyZWVfd29yayBvbiB0aGUgZ2xvYmFs IHN5c3RlbQp3b3JrcXVldWUuIElmIGEgRE1BIGNoYW5uZWwgaXMgZnJlZWQganVzdCBiZWZvcmUg b3IgZHVyaW5nIG1vZHVsZSB1bmxvYWQsCnRoZSBzY2hlZHVsZWQgd29yayBpcyBub3QgZmx1c2hl ZCBvciB3YWl0ZWQgdXBvbiBiZWZvcmUgZGV2cmVzIGRyb3BzIHRoZQpiYWNraW5nIG1lbW9yeS4K ClRoZSBhc3luY2hyb25vdXMgd29yayB3aWxsIGV4ZWN1dGUgYWZ0ZXIgYW1sX2RtYSBpcyBmcmVl ZCwgZGVyZWZlcmVuY2luZyBhCmRhbmdsaW5nIHBvaW50ZXIuCgo+ICsKPiArCWZvciAoaSA9IDA7 IGkgPCBNQVhfQ0hBTl9JRDsgaSsrKSB7Cj4gKwkJYW1sX2NoYW4gPSBhbWxfZG1hLT5hbWxfcmNo W2ldOwo+ICsJCWlmIChhbWxfY2hhbikKPiArCQkJdGFza2xldF9raWxsKCZhbWxfY2hhbi0+dmNo YW4udGFzayk7Cj4gKwkJYW1sX2NoYW4gPSBhbWxfZG1hLT5hbWxfd2NoW2ldOwo+ICsJCWlmIChh bWxfY2hhbikKPiArCQkJdGFza2xldF9raWxsKCZhbWxfY2hhbi0+dmNoYW4udGFzayk7Cj4gKwl9 Cj4gK30KCltTZXZlcml0eTogSGlnaF0KRG9lcyBraWxsaW5nIHRhc2tsZXRzIGhlcmUgd2l0aG91 dCBJUlEgc3luY2hyb25pemF0aW9uIGV4cG9zZSBhIHJhY2Ugd2luZG93PwoKQmVjYXVzZSBkZXZt X3JlcXVlc3RfaXJxKCkgaXMgdXNlZCwgdGhlIGludGVycnVwdCBpcyBmcmVlZCBieSBkZXZyZXMg YWZ0ZXIKcmVtb3ZlKCkgY29tcGxldGVzLiBJZiBhbiBpbnRlcnJ1cHQgaGFuZGxlciBpcyBhY3Rp dmVseSBleGVjdXRpbmcgb24gYW5vdGhlcgpDUFUsIGl0IGNhbiBjYWxsIHRhc2tsZXRfc2NoZWR1 bGUoKSBpbW1lZGlhdGVseSBhZnRlciB0YXNrbGV0X2tpbGwoKQpmaW5pc2hlcy4KCkRldnJlcyB0 aGVuIGZyZWVzIHRoZSBzdHJ1Y3R1cmVzLCBhbmQgdGhlIG5ld2x5IHNjaGVkdWxlZCB0YXNrbGV0 IHdpbGwgbGF0ZXIKZXhlY3V0ZSBvbiBmcmVlZCBtZW1vcnkgaW4gdGhlIHNvZnRpcnEgY29udGV4 dC4gV291bGQgY2FsbGluZwpzeW5jaHJvbml6ZV9pcnEoKSBiZWZvcmUga2lsbGluZyB0YXNrbGV0 cyBwcmV2ZW50IHRoaXM/CgotLSAKU2FzaGlrbyBBSSByZXZpZXcgwrcgaHR0cHM6Ly9zYXNoaWtv LmRldi8jL3BhdGNoc2V0LzIwMjYwNzEwLWFtbG9naWMtZG1hLXYxMC0wLWZmNGRlYWU4MzdlN0Bh bWxvZ2ljLmNvbT9wYXJ0PTIKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fCmxpbnV4LWFtbG9naWMgbWFpbGluZyBsaXN0CmxpbnV4LWFtbG9naWNAbGlzdHMu aW5mcmFkZWFkLm9yZwpodHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZv L2xpbnV4LWFtbG9naWMK