From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C010DC43458 for ; Sat, 11 Jul 2026 22:41:20 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wigNO-0004HF-FP; Sat, 11 Jul 2026 18:40:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wigNJ-00043v-Hy; Sat, 11 Jul 2026 18:40:45 -0400 Received: from pdx-out-003.esa.us-west-2.outbound.mail-perimeter.amazon.com ([44.246.68.102]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wigNF-0005mg-Kr; Sat, 11 Jul 2026 18:40:45 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazoncorp2; t=1783809641; x=1815345641; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8qB3yVqVzEHdcQcyvRloVub+hLfEuv5n21OR2C+g0CU=; b=O0fVth1pzSzpLoc7etW0tmUqTjGXrcM138jUFYbinMQbgOOwLvxSUQxZ ZY3DfRht/NlsfscN1cSwlNf+DggfU/YFhhiRqueRm+9r55X+Ue8XAdBm/ XtR9tJlFhX6U2kY7mGOBSDrA/wQFLYTksjVSYMo8yE4Zvi2NqjwyqzHHj ZueazEIMyNawKmjzY8BmlTQv2A8NZlfrBjRyFK3PoUICyCsaCXi1/6ZRG qUQQ7gKgd7BkWywR5OL+laZ11BVuL7s+HD/RwoObszmJbpyDJiKgUxqy1 ritI+gk5QbDHycyTtnZpbOmGCEwxi8qynTvTT+I/X3i6VGa+HM2lx+P0h w==; X-CSE-ConnectionGUID: mhBJrtIQR7GXKYwYvwUE/Q== X-CSE-MsgGUID: kUFf/vlYS06QlpXKX5gf7w== X-IronPort-AV: E=Sophos;i="6.25,154,1779148800"; d="scan'208";a="23517015" Received: from ip-10-5-12-219.us-west-2.compute.internal (HELO smtpout.naws.us-west-2.prod.farcaster.email.amazon.dev) ([10.5.12.219]) by internal-pdx-out-003.esa.us-west-2.outbound.mail-perimeter.amazon.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jul 2026 22:40:37 +0000 Received: from EX19MTAUWC002.ant.amazon.com [205.251.233.111:8026] by smtpin.naws.us-west-2.prod.farcaster.email.amazon.dev [10.0.35.214:2525] with esmtp (Farcaster) id b54a1bf2-3fb6-4c80-8bc5-1137b2e286ce; Sat, 11 Jul 2026 22:40:37 +0000 (UTC) X-Farcaster-Flow-ID: b54a1bf2-3fb6-4c80-8bc5-1137b2e286ce Received: from EX19D001UWA001.ant.amazon.com (10.13.138.214) by EX19MTAUWC002.ant.amazon.com (10.250.64.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA) id 15.2.2562.43; Sat, 11 Jul 2026 22:40:36 +0000 Received: from ip-10-253-83-51.amazon.com (172.19.99.218) by EX19D001UWA001.ant.amazon.com (10.13.138.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA) id 15.2.2562.43; Sat, 11 Jul 2026 22:40:28 +0000 From: Alexander Graf To: CC: , , , , Song Gao <17746591750@163.com>, Aditya Gupta , Alexey Kardashevskiy , Farhan Ali , Alistair Francis , "Alistair Francis" , Antony Pavlov , Markus Armbruster , Artyom Tarasenko , BALATON Zoltan , Felipe Balbi , Christian Borntraeger , "Brian Cain" , Hendrik Brueckner , Chao Liu , "Huacai Chen" , =?UTF-8?q?Cl=C3=A9ment=20Chigot?= , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Helge Deller , Dorjoy Chowdhury , "Edgar E . Iglesias" , Alexandre Iooss , Eric Farman , Francisco Iglesias , Gaurav Sharma , "Gautam Gala" , Harsh Prateek Bora , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Jan Kiszka , Max Filippov , Joel Stanley , Jared Rossi , Tyrone Ting , Frederic Konrad , "Laurent Vivier" , Manos Pitsidianakis , Bibo Mao , "Mark Cave-Ayland" , Glenn Miles , Matthew Rosato , "Michael Rolnik" , "Michael S . Tsirkin" , "Niek Linnenbank" , Nicholas Piggin , Palmer Dabbelt , Halil Pasic , "Paolo Bonzini" , Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Pierrick Bouvier" , Richard Henderson , Sai Pavan Boddu , Samuel Tardieu , Bernhard Beschow , Stafford Horne , Sergio Lopez , "Subbaraya Sundeep" , Thomas Huth , "Ran Wang" , Hao Wu , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= Subject: [RFC PATCH 013/134] hw/alpha: Give onboard devices a QOM parent Date: Sat, 11 Jul 2026 22:35:06 +0000 Message-ID: <20260711223707.42139-14-graf@amazon.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20260711223707.42139-1-graf@amazon.com> References: <20260711223707.42139-1-graf@amazon.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.19.99.218] X-ClientProxiedBy: EX19D031UWC004.ant.amazon.com (10.13.139.246) To EX19D001UWA001.ant.amazon.com (10.13.138.214) Received-SPF: pass client-ip=44.246.68.102; envelope-from=prvs=645f258d4=graf@amazon.de; helo=pdx-out-003.esa.us-west-2.outbound.mail-perimeter.amazon.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.445, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, T_SPF_PERMERROR=0.01, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Convert the *_orphan() device-creation calls in hw/alpha to the new parented API introduced earlier in this series, so every onboard device gets a stable path in the composition tree instead of landing in /machine/unattached with an unstable device[N] name. The parent for each device is the object that owns its lifetime: the machine for board-created devices, the containing device for composite children. Names follow existing QOM conventions. Per-site rationale (reviewers: dispute the modeling here): file:line | parent | name | rationale dp264.c:68 | OBJECT(machine) | "cpu[*]" | SMP CPUs created by board init() dp264.c:113 | OBJECT(machine) | "isa-bridge" | i82378 PCI-ISA bridge is a fixed onboard device; the machine owns it dp264.c:129 | OBJECT(machine) | "sio" | SMC37C669 Super-I/O is a fixed onboard device dp264.c:132 | OBJECT(machine) | "ide" | CMD646 IDE controller is a fixed onboard device typhoon.c:833 | OBJECT(machine) | "typhoon" | Typhoon PCI host bridge is a fixed chipset of the DP264 board; thread an Object *parent argument through typhoon_init() from clipper_init() Link: https://lore.kernel.org/qemu-devel/87jyr3w9tc.fsf@pond.sub.org/ Assisted-by: Kiro Signed-off-by: Alexander Graf --- hw/alpha/alpha_sys.h | 3 ++- hw/alpha/dp264.c | 12 +++++++----- hw/alpha/typhoon.c | 6 +++--- 3 files changed, 12 insertions(+), 9 deletions(-) diff --git a/hw/alpha/alpha_sys.h b/hw/alpha/alpha_sys.h index 6e6691d116..f8aaf74933 100644 --- a/hw/alpha/alpha_sys.h +++ b/hw/alpha/alpha_sys.h @@ -9,7 +9,8 @@ #include "hw/intc/i8259.h" -PCIBus *typhoon_init(MemoryRegion *, qemu_irq *, qemu_irq *, AlphaCPU *[4], +PCIBus *typhoon_init(Object *parent, MemoryRegion *, + qemu_irq *, qemu_irq *, AlphaCPU *[4], pci_map_irq_fn, uint8_t devfn_min); /* alpha_pci.c. */ diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c index 512b270838..9cd448cff1 100644 --- a/hw/alpha/dp264.c +++ b/hw/alpha/dp264.c @@ -49,6 +49,7 @@ static void clipper_init(MachineState *machine) const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; MachineClass *mc = MACHINE_GET_CLASS(machine); + Object *mo = OBJECT(machine); AlphaCPU *cpus[4]; PCIBus *pci_bus; PCIDevice *pci_dev; @@ -65,7 +66,7 @@ static void clipper_init(MachineState *machine) /* Create up to 4 cpus. */ memset(cpus, 0, sizeof(cpus)); for (i = 0; i < smp_cpus; ++i) { - cpus[i] = ALPHA_CPU(cpu_create_orphan(machine->cpu_type)); + cpus[i] = ALPHA_CPU(cpu_create(mo, "cpu[*]", machine->cpu_type)); } /* @@ -86,7 +87,7 @@ static void clipper_init(MachineState *machine) * Init the chipset. Because we're using CLIPPER IRQ mappings, * the minimum PCI device IdSel is 1. */ - pci_bus = typhoon_init(machine->ram, &isa_irq, &rtc_irq, cpus, + pci_bus = typhoon_init(mo, machine->ram, &isa_irq, &rtc_irq, cpus, clipper_pci_map_irq, PCI_DEVFN(1, 0)); /* @@ -110,7 +111,8 @@ static void clipper_init(MachineState *machine) * Importantly, we need to provide a PCI device node for it, otherwise * some operating systems won't notice there's an ISA bus to configure. */ - i82378_dev = DEVICE(pci_create_simple_orphan(pci_bus, PCI_DEVFN(7, 0), "i82378")); + i82378_dev = DEVICE(pci_create_simple(mo, "isa-bridge", pci_bus, + PCI_DEVFN(7, 0), "i82378")); isa_bus = ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0")); /* Connect the ISA PIC to the Typhoon IRQ used for ISA interrupts. */ @@ -126,10 +128,10 @@ static void clipper_init(MachineState *machine) pci_init_nic_devices(pci_bus, mc->default_nic); /* Super I/O */ - isa_create_simple_orphan(isa_bus, TYPE_SMC37C669_SUPERIO); + isa_create_simple(mo, "sio", isa_bus, TYPE_SMC37C669_SUPERIO); /* IDE disk setup. */ - pci_dev = pci_create_simple_orphan(pci_bus, -1, "cmd646-ide"); + pci_dev = pci_create_simple(mo, "ide", pci_bus, -1, "cmd646-ide"); pci_ide_create_devs(pci_dev); /* Load PALcode. Given that this is not "real" cpu palcode, diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c index af40647ccd..af39f2659b 100644 --- a/hw/alpha/typhoon.c +++ b/hw/alpha/typhoon.c @@ -819,7 +819,7 @@ static void typhoon_alarm_timer(void *opaque) cpu_interrupt(CPU(s->cchip.cpu[cpu]), CPU_INTERRUPT_TIMER); } -PCIBus *typhoon_init(MemoryRegion *ram, qemu_irq *p_isa_irq, +PCIBus *typhoon_init(Object *parent, MemoryRegion *ram, qemu_irq *p_isa_irq, qemu_irq *p_rtc_irq, AlphaCPU *cpus[4], pci_map_irq_fn sys_map_irq, uint8_t devfn_min) { @@ -830,7 +830,7 @@ PCIBus *typhoon_init(MemoryRegion *ram, qemu_irq *p_isa_irq, PCIBus *b; int i; - dev = qdev_new_orphan(TYPE_TYPHOON_PCI_HOST_BRIDGE); + dev = qdev_new(parent, "typhoon", TYPE_TYPHOON_PCI_HOST_BRIDGE); s = TYPHOON_PCI_HOST_BRIDGE(dev); phb = PCI_HOST_BRIDGE(dev); @@ -894,7 +894,7 @@ PCIBus *typhoon_init(MemoryRegion *ram, qemu_irq *p_isa_irq, &s->pchip.reg_mem, &s->pchip.reg_io, devfn_min, 64, TYPE_PCI_BUS); phb->bus = b; - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); /* Host memory as seen from the PCI side, via the IOMMU. */ memory_region_init_iommu(&s->pchip.iommu, sizeof(s->pchip.iommu), -- 2.47.1