From: Mohamed Khalfella <mkhalfella@purestorage.com>
To: Justin Tee <justin.tee@broadcom.com>,
Naresh Gottumukkala <nareshgottumukkala83@gmail.com>,
Paul Ely <paul.ely@broadcom.com>,
Chaitanya Kulkarni <kch@nvidia.com>,
Christoph Hellwig <hch@lst.de>, Jens Axboe <axboe@kernel.dk>,
Keith Busch <kbusch@kernel.org>, Sagi Grimberg <sagi@grimberg.me>,
James Smart <jsmart833426@gmail.com>,
Hannes Reinecke <hare@suse.de>,
Randy Jennings <randyj@purestorage.com>,
Dhaval Giani <dgiani@purestorage.com>
Cc: Aaron Dailey <adailey@purestorage.com>,
linux-nvme@lists.infradead.org, linux-kernel@vger.kernel.org,
Mohamed Khalfella <mkhalfella@purestorage.com>
Subject: [PATCH v5 15/16] nvmet: Add support for CQT to nvme target
Date: Sat, 11 Jul 2026 19:23:36 -0700 [thread overview]
Message-ID: <20260712022437.3743117-16-mkhalfella@purestorage.com> (raw)
In-Reply-To: <20260712022437.3743117-1-mkhalfella@purestorage.com>
TP4129 KATO Corrections and Clarifications defined CQT (Command Quiesce
Time) which is used along with KATO (Keep Alive Timeout) to set an upper
time limit for attempting Cross-Controller Recovery. CQT is added as a
subsystem attribute that defaults to 0 to maintain the current behavior.
Signed-off-by: Mohamed Khalfella <mkhalfella@purestorage.com>
---
drivers/nvme/target/admin-cmd.c | 1 +
drivers/nvme/target/configfs.c | 36 +++++++++++++++++++++++++++++++++
drivers/nvme/target/core.c | 3 +++
drivers/nvme/target/nvmet.h | 2 ++
include/linux/nvme.h | 5 ++++-
5 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/drivers/nvme/target/admin-cmd.c b/drivers/nvme/target/admin-cmd.c
index ea2566a9b83f..fbfc226c9830 100644
--- a/drivers/nvme/target/admin-cmd.c
+++ b/drivers/nvme/target/admin-cmd.c
@@ -737,6 +737,7 @@ static void nvmet_execute_identify_ctrl(struct nvmet_req *req)
id->cntlid = cpu_to_le16(ctrl->cntlid);
id->ver = cpu_to_le32(ctrl->subsys->ver);
if (!nvmet_is_disc_subsys(ctrl->subsys)) {
+ id->cqt = cpu_to_le16(ctrl->cqt);
id->ciu = ctrl->ciu;
id->cirn = cpu_to_le64(ctrl->cirn);
id->ccrl = NVMF_CCR_LIMIT;
diff --git a/drivers/nvme/target/configfs.c b/drivers/nvme/target/configfs.c
index 2b69ffcfc8df..b99f31c0a640 100644
--- a/drivers/nvme/target/configfs.c
+++ b/drivers/nvme/target/configfs.c
@@ -1661,6 +1661,41 @@ static ssize_t nvmet_subsys_attr_pi_enable_store(struct config_item *item,
CONFIGFS_ATTR(nvmet_subsys_, attr_pi_enable);
#endif
+static ssize_t nvmet_subsys_attr_cqt_show(struct config_item *item,
+ char *page)
+{
+ return snprintf(page, PAGE_SIZE, "%u\n", to_subsys(item)->cqt);
+}
+
+static ssize_t nvmet_subsys_attr_cqt_store(struct config_item *item,
+ const char *page, size_t cnt)
+{
+ struct nvmet_subsys *subsys = to_subsys(item);
+ struct nvmet_ctrl *ctrl;
+ u16 cqt;
+
+ if (nvmet_is_disc_subsys(subsys))
+ return -EINVAL;
+
+ if (sscanf(page, "%hu\n", &cqt) != 1)
+ return -EINVAL;
+
+ down_write(&nvmet_config_sem);
+ mutex_lock(&subsys->lock);
+ if (subsys->cqt == cqt)
+ goto out;
+
+ subsys->cqt = cqt;
+ /* Force reconnect */
+ list_for_each_entry(ctrl, &subsys->ctrls, subsys_entry)
+ ctrl->ops->delete_ctrl(ctrl);
+out:
+ mutex_unlock(&subsys->lock);
+ up_write(&nvmet_config_sem);
+ return cnt;
+}
+CONFIGFS_ATTR(nvmet_subsys_, attr_cqt);
+
static ssize_t nvmet_subsys_attr_qid_max_show(struct config_item *item,
char *page)
{
@@ -1701,6 +1736,7 @@ static struct configfs_attribute *nvmet_subsys_attrs[] = {
&nvmet_subsys_attr_attr_vendor_id,
&nvmet_subsys_attr_attr_subsys_vendor_id,
&nvmet_subsys_attr_attr_model,
+ &nvmet_subsys_attr_attr_cqt,
&nvmet_subsys_attr_attr_qid_max,
&nvmet_subsys_attr_attr_ieee_oui,
&nvmet_subsys_attr_attr_firmware,
diff --git a/drivers/nvme/target/core.c b/drivers/nvme/target/core.c
index 9b16b15f5093..e59026ca449f 100644
--- a/drivers/nvme/target/core.c
+++ b/drivers/nvme/target/core.c
@@ -1729,6 +1729,7 @@ struct nvmet_ctrl *nvmet_alloc_ctrl(struct nvmet_alloc_ctrl_args *args)
ctrl->cntlid = ret;
if (!nvmet_is_disc_subsys(ctrl->subsys)) {
+ ctrl->cqt = subsys->cqt;
ctrl->ciu = get_random_u8() ? : 1;
ctrl->cirn = get_random_u64();
}
@@ -1969,10 +1970,12 @@ struct nvmet_subsys *nvmet_subsys_alloc(const char *subsysnqn,
switch (type) {
case NVME_NQN_NVME:
+ subsys->cqt = NVMF_CQT_MS;
subsys->max_qid = NVMET_NR_QUEUES;
break;
case NVME_NQN_DISC:
case NVME_NQN_CURR:
+ subsys->cqt = 0;
subsys->max_qid = 0;
break;
default:
diff --git a/drivers/nvme/target/nvmet.h b/drivers/nvme/target/nvmet.h
index da80377c3795..4ff458c3ccdc 100644
--- a/drivers/nvme/target/nvmet.h
+++ b/drivers/nvme/target/nvmet.h
@@ -269,6 +269,7 @@ struct nvmet_ctrl {
uuid_t hostid;
u16 cntlid;
+ u16 cqt;
u8 ciu;
u32 kato;
u64 cirn;
@@ -346,6 +347,7 @@ struct nvmet_subsys {
#ifdef CONFIG_NVME_TARGET_DEBUGFS
struct dentry *debugfs_dir;
#endif
+ u16 cqt;
u16 max_qid;
u64 ver;
diff --git a/include/linux/nvme.h b/include/linux/nvme.h
index 3757d11ffea3..0b69ed53f347 100644
--- a/include/linux/nvme.h
+++ b/include/linux/nvme.h
@@ -21,6 +21,7 @@
#define NVMF_TRADDR_SIZE 256
#define NVMF_TSAS_SIZE 256
+#define NVMF_CQT_MS 0
#define NVMF_CCR_LIMIT 4
#define NVMF_CCR_PER_PAGE 511
@@ -368,7 +369,9 @@ struct nvme_id_ctrl {
__u8 anacap;
__le32 anagrpmax;
__le32 nanagrpid;
- __u8 rsvd352[160];
+ __u8 rsvd352[34];
+ __le16 cqt;
+ __u8 rsvd388[124];
__u8 sqes;
__u8 cqes;
__le16 maxcmd;
--
2.54.0
next prev parent reply other threads:[~2026-07-12 2:25 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-12 2:23 [PATCH v5 00/16] TP8028 Rapid Path Failure Recovery Mohamed Khalfella
2026-07-12 2:23 ` [PATCH v5 01/16] nvmet: Rapid Path Failure Recovery set controller identify fields Mohamed Khalfella
2026-07-12 2:23 ` [PATCH v5 02/16] nvmet/debugfs: Export controller CIU and CIRN via debugfs Mohamed Khalfella
2026-07-12 2:23 ` [PATCH v5 03/16] nvmet: Implement CCR nvme command Mohamed Khalfella
2026-07-12 2:23 ` [PATCH v5 04/16] nvmet: Implement CCR logpage Mohamed Khalfella
2026-07-12 2:23 ` [PATCH v5 05/16] nvmet: Send an AEN on CCR completion Mohamed Khalfella
2026-07-12 2:23 ` [PATCH v5 06/16] nvme: Rapid Path Failure Recovery read controller identify fields Mohamed Khalfella
2026-07-12 2:23 ` [PATCH v5 07/16] nvme: Introduce FENCING and FENCED controller states Mohamed Khalfella
2026-07-12 2:23 ` [PATCH v5 08/16] nvme: Implement cross-controller reset recovery Mohamed Khalfella
2026-07-13 7:04 ` Hannes Reinecke
2026-07-12 2:23 ` [PATCH v5 09/16] nvme: Implement cross-controller reset completion Mohamed Khalfella
2026-07-13 7:11 ` Hannes Reinecke
2026-07-12 2:23 ` [PATCH v5 10/16] nvme-tcp: Use CCR to recover controller that hits an error Mohamed Khalfella
2026-07-13 7:17 ` Hannes Reinecke
2026-07-12 2:23 ` [PATCH v5 11/16] nvme-rdma: " Mohamed Khalfella
2026-07-13 7:18 ` Hannes Reinecke
2026-07-12 2:23 ` [PATCH v5 12/16] nvme-fc: Refactor IO error recovery Mohamed Khalfella
2026-07-13 7:29 ` Hannes Reinecke
2026-07-12 2:23 ` [PATCH v5 13/16] nvme-fc: Use CCR to recover controller that hits an error Mohamed Khalfella
2026-07-12 2:23 ` [PATCH v5 14/16] nvme-fc: Hold inflight requests while in FENCING state Mohamed Khalfella
2026-07-12 2:23 ` Mohamed Khalfella [this message]
2026-07-13 7:35 ` [PATCH v5 15/16] nvmet: Add support for CQT to nvme target Hannes Reinecke
2026-07-12 2:23 ` [PATCH v5 16/16] nvme: Add support for CQT to nvme host Mohamed Khalfella
2026-07-13 7:36 ` Hannes Reinecke
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