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From: sashiko-bot@kernel.org
To: "Junhui Liu" <junhui.liu@pigmoral.tech>
Cc: robh@kernel.org, conor+dt@kernel.org,
	linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org
Subject: Re: [PATCH v2 8/8] clk: sunxi-ng: a733: Add reset lines
Date: Sun, 12 Jul 2026 08:13:44 +0000	[thread overview]
Message-ID: <20260712081344.7533A1F00A3A@smtp.kernel.org> (raw)
In-Reply-To: <20260711-a733-clk-v2-8-974d188cbe0c@pigmoral.tech>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The `sun60i_a733_ccu_resets` array is missing the `const` qualifier.
--

--- Patch [8]: [PATCH v2 8/8] clk: sunxi-ng: a733: Add reset lines ---
commit 4ea86ec36599a9ad729bf576a38c2f6cad725b56
Author: Junhui Liu <junhui.liu@pigmoral.tech>

clk: sunxi-ng: a733: Add reset lines

This patch adds the reset lines for the Allwinner A733 SoC. The reset control
bits are integrated into the main CCU driver using the sunxi-ng ccu_reset
framework, enabling the CCU to function as a reset controller.

> diff --git a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c
> index 48d7c0395ae83..ff64c35206d2d 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun60i-a733.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun60i-a733.c

[ ... ]

> @@ -2156,11 +2157,136 @@ static struct clk_hw_onecell_data sun60i_a733_hw_clks = {
>  	.num	= CLK_FANOUT3 + 1,
>  };
>  
> +static struct ccu_reset_map sun60i_a733_ccu_resets[] = {

[Severity: Low]
Is it possible to add the const qualifier to the sun60i_a733_ccu_resets array?

Without the const qualifier, this reset map array is placed in the mutable
.data section instead of the read-only .rodata section. Because it is later
assigned to the .resets member of sunxi_ccu_desc which expects a const pointer,
adding const here would save mutable memory and slightly improve security
hardening.

> +	[RST_BUS_ITS_PCIE0]		= { 0x574, BIT(16) },
> +	[RST_BUS_IOMMU0_SYS]		= { 0x58c, BIT(16) },

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260711-a733-clk-v2-0-974d188cbe0c@pigmoral.tech?part=8

      reply	other threads:[~2026-07-12  8:13 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-11  8:10 [PATCH v2 0/8] clk: sunxi-ng: Add support for Allwinner A733 CCU and PRCM Junhui Liu
2026-07-11  8:10 ` Junhui Liu
2026-07-11  8:10 ` [PATCH v2 1/8] dt-bindings: clk: sun60i-a733-ccu: Add allwinner A733 support Junhui Liu
2026-07-11  8:10   ` Junhui Liu
2026-07-12  8:13   ` sashiko-bot
2026-07-12 14:35   ` Krzysztof Kozlowski
2026-07-12 14:35     ` Krzysztof Kozlowski
2026-07-11  8:10 ` [PATCH v2 2/8] clk: sunxi-ng: sdm: Add dual patterns support Junhui Liu
2026-07-11  8:10   ` Junhui Liu
2026-07-11  8:10 ` [PATCH v2 3/8] clk: sunxi-ng: a733: Add PRCM CCU Junhui Liu
2026-07-11  8:10   ` Junhui Liu
2026-07-12  8:13   ` sashiko-bot
2026-07-11  8:10 ` [PATCH v2 4/8] clk: sunxi-ng: a733: Add PLL clocks support Junhui Liu
2026-07-11  8:10   ` Junhui Liu
2026-07-12  8:13   ` sashiko-bot
2026-07-11  8:10 ` [PATCH v2 5/8] clk: sunxi-ng: a733: Add bus " Junhui Liu
2026-07-11  8:10   ` Junhui Liu
2026-07-12  8:13   ` sashiko-bot
2026-07-11  8:10 ` [PATCH v2 6/8] clk: sunxi-ng: a733: Add mod " Junhui Liu
2026-07-11  8:10   ` Junhui Liu
2026-07-12  8:13   ` sashiko-bot
2026-07-12 14:25   ` Junhui Liu
2026-07-12 14:25     ` Junhui Liu
2026-07-11  8:10 ` [PATCH v2 7/8] clk: sunxi-ng: a733: Add bus clock gates Junhui Liu
2026-07-11  8:10   ` Junhui Liu
2026-07-12  8:13   ` sashiko-bot
2026-07-12 14:29   ` Junhui Liu
2026-07-12 14:29     ` Junhui Liu
2026-07-11  8:10 ` [PATCH v2 8/8] clk: sunxi-ng: a733: Add reset lines Junhui Liu
2026-07-11  8:10   ` Junhui Liu
2026-07-12  8:13   ` sashiko-bot [this message]

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