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[84.0.19.134]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-493eb6df417sm387974995e9.8.2026.07.13.06.07.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jul 2026 06:07:24 -0700 (PDT) From: =?UTF-8?q?Timur=20Krist=C3=B3f?= To: amd-gfx@lists.freedesktop.org, Alex Deucher , christian.koenig@amd.com, Tvrtko Ursulin , pierre-eric.pelloux-prayer@amd.com, Natalie Vock Cc: =?UTF-8?q?Timur=20Krist=C3=B3f?= Subject: [PATCH 05/11] drm/amdgpu/gfx6: Clean up rings during reset Date: Mon, 13 Jul 2026 15:07:03 +0200 Message-ID: <20260713130709.34262-6-timur.kristof@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260713130709.34262-1-timur.kristof@gmail.com> References: <20260713130709.34262-1-timur.kristof@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Clear the WPTR and RPTR at ring initialization. Additionally clear the ring contents during reset. This is necessary so that the IP block soft reset can bring the rings back to a clean state. Signed-off-by: Timur Kristóf --- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 28 +++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index ca6a62e822b1..eeada89bb31a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -2158,8 +2158,14 @@ static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev) WREG32(mmSCRATCH_ADDR, 0); /* ring 0 - compute and gfx */ - /* Set ring buffer size */ ring = &adev->gfx.gfx_ring[0]; + atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); + atomic64_set((atomic64_t *)ring->rptr_cpu_addr, 0); + + if (amdgpu_in_reset(adev)) + amdgpu_ring_clear_ring(ring); + + /* Set ring buffer size */ rb_bufsz = order_base_2(ring->ring_size / 8); tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; @@ -2171,7 +2177,8 @@ static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev) /* Initialize the ring buffer's read and write pointers */ WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); ring->wptr = 0; - WREG32(mmCP_RB0_WPTR, ring->wptr); + WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); + WREG32(mmCP_RB0_RPTR, lower_32_bits(ring->wptr)); /* set the wb address whether it's enabled or not */ rptr_addr = ring->rptr_gpu_addr; @@ -2188,6 +2195,11 @@ static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev) /* ring 1 - compute only */ if (adev->gfx.num_compute_rings >= 1) { ring = &adev->gfx.compute_ring[0]; + atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); + atomic64_set((atomic64_t *)ring->rptr_cpu_addr, 0); + + if (amdgpu_in_reset(adev)) + amdgpu_ring_clear_ring(ring); rb_bufsz = order_base_2(ring->ring_size / 8); tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE / 8) << 8) | rb_bufsz; @@ -2198,7 +2210,8 @@ static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev) WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK); ring->wptr = 0; - WREG32(mmCP_RB1_WPTR, ring->wptr); + WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); + WREG32(mmCP_RB1_RPTR, lower_32_bits(ring->wptr)); rptr_addr = ring->rptr_gpu_addr; WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); @@ -2212,6 +2225,11 @@ static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev) /* ring 2 - compute only */ if (adev->gfx.num_compute_rings >= 2) { ring = &adev->gfx.compute_ring[1]; + atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); + atomic64_set((atomic64_t *)ring->rptr_cpu_addr, 0); + + if (amdgpu_in_reset(adev)) + amdgpu_ring_clear_ring(ring); rb_bufsz = order_base_2(ring->ring_size / 8); tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE / 8) << 8) | rb_bufsz; @@ -2222,7 +2240,9 @@ static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev) WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK); ring->wptr = 0; - WREG32(mmCP_RB2_WPTR, ring->wptr); + WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr)); + WREG32(mmCP_RB2_RPTR, lower_32_bits(ring->wptr)); + rptr_addr = ring->rptr_gpu_addr; WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr)); WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); -- 2.55.0