Re: [PATCH 2/2] arm64: dts: qcom: shikra: Add coresight nodes

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The ETM device tree nodes use the `arm,coresight-etm4x-sysreg` compatible string while simultaneously specifying a memory-mapped `reg` property, which inadvertently forces the Linux driver to use MMIO and bypasses sysreg access.
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--- Patch [2]: [PATCH 2/2] arm64: dts: qcom: shikra: Add coresight nodes ---
commit 24d3e76ff822f220e7ce3ce7c925342e5bd6c189
Author: Jie Gan <jie.gan@oss.qualcomm.com>

arm64: dts: qcom: shikra: Add coresight nodes

This commit adds DT nodes for the CoreSight debug and trace subsystem on the
Qualcomm Shikra SoC.

> diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
> index 4e5bc9e17c8ed..84c906be16a93 100644
> --- a/arch/arm64/boot/dts/qcom/shikra.dtsi
> +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi

[ ... ]

> +		etm@9040000 {
> +			compatible = "arm,coresight-etm4x-sysreg";
> +			reg = <0x0 0x09040000 0x0 0x1000>;

[Severity: High]
Does combining "arm,coresight-etm4x-sysreg" with a memory-mapped reg property
cause the driver to incorrectly fall back to MMIO mode?

Since this compatible string is meant for sysreg-only access, providing the
reg property violates the DT bindings. This forces the coresight-etm4x
platform driver into an MMIO fallback mode and skips sysreg initialization.

Because it binds to the platform driver instead of the AMBA primecell driver,
won't it miss AMBA PM and UCI ID initialization? Accessing an unpowered or
improperly clocked CoreSight MMIO region could cause bus errors or silent
probe failures.

This same pattern also appears in the other ETM nodes added by this patch
(etm@9140000, etm@9240000, and etm@9340000).

> +
> +			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
> +			clock-names = "apb_pclk";
> +			cpu = <&cpu0>;
> +			qcom,skip-power-up;

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Sashiko AI review · https://sashiko.dev/#/patchset/20260714-add-coresight-nodes-for-shikra-v1-0-b1cf85962455@oss.qualcomm.com?part=2