Re: [PATCH 1/2] arm64: dts: qcom: ipq9650: add the PCIe support

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The `gcc` node is missing the `#interconnect-cells = <1>;` property, which causes interconnect parsing for all PCIe controllers to fail.
--

--- Patch [1]: [PATCH 1/2] arm64: dts: qcom: ipq9650: add the PCIe support ---
commit 568f2d4c0bdec47be174d592deb75c6d379fe4dd
Author: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>

arm64: dts: qcom: ipq9650: add the PCIe support
    
IPQ9650 has 5 Gen3 PCIe controllers - PCIe0 and PCIe4 are single lane
and the remaining instances are dual lane. Add support for the same.

> diff --git a/arch/arm64/boot/dts/qcom/ipq9650.dtsi b/arch/arm64/boot/dts/qcom/ipq9650.dtsi
> index 3d3b317c6a3cc..8301a4090395e 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9650.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9650.dtsi
[ ... ]
> @@ -216,11 +371,11 @@ gcc: clock-controller@1800000 {
>  			reg = <0x0 0x01800000 0x0 0x40000>;
>  			clocks = <&xo_board>,
>  				 <&sleep_clk>,
> -				 <0>,
> -				 <0>,
> -				 <0>,
> -				 <0>,
> -				 <0>,
> +				 <&pcie0_phy>,
> +				 <&pcie1_phy>,
> +				 <&pcie2_phy>,
> +				 <&pcie3_phy>,
> +				 <&pcie4_phy>,
>  				 <0>,
>  				 <0>;
>  			#clock-cells = <1>;

[Severity: High]
Does this gcc node need an #interconnect-cells = <1>; property?

The new PCIe nodes declare interconnects pointing to the gcc node.

When the PCIe controller driver attempts to acquire these interconnects
during probe via devm_of_icc_get(), the core interconnect code calls
of_parse_phandle_with_args().

If the target gcc node lacks the #interconnect-cells property, parsing
fails and returns -EINVAL. This will cause PCIe initialization to fail
entirely for all 5 controllers.

[ ... ]
> @@ -371,6 +526,506 @@ frame@f42d000 {
[ ... ]
> +		pcie3: pcie@30000000 {
> +			compatible = "qcom,pcie-ipq9650", "qcom,pcie-ipq9574";
[ ... ]
> +			interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>,
> +					<&gcc MASTER_CNOC_PCIE3 &gcc SLAVE_CNOC_PCIE3>;
> +			interconnect-names = "pcie-mem", "cpu-pcie";
> +
> +			status = "disabled";

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260714-ipq9650_pcie-v1-0-4197749d06bd@oss.qualcomm.com?part=1