From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8F961C43458 for ; Tue, 14 Jul 2026 08:22:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Reply-To:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: References:In-Reply-To:Cc:To:Subject:From:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=mtpytCAzfb0xZKHGf0NLNaXorsWEp/I5Qo4ZIDE312U=; b=MDkt9RmFcq0lI0 okx/mBjQr0tLqS1iBNfuhlxiGLC21JlDSmz1eyGXFesbFc0Ql2s0sR3+gyhvptoZ8KKyKui9noOPX VTzkUWdGnVYZx1s8tpt3q7v6h1Bdr7rT9dMI1nT4YimNH4ay969+oMTtxsBrZDP9lQxdG6P1SniX2 E9j1EbDl1Wv5F+dzKGkKnPDHnbi16B8OlsjXKWZovhRQ1y0D4HZyNQTq42SOKf3KEEbCk3l6Omr5y h5AwBSnzMhWevVKZA8EKA2Fcmo2eyPfO/tJ8nBNoTgh7vFHaxFaZj20RgCx3e5dbzogRwYEq1Ar0g YRSd0LcQO3d6/2+5iNOQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wjYPE-0000000BHwP-0IOV; Tue, 14 Jul 2026 08:22:20 +0000 Received: from tor.source.kernel.org ([172.105.4.254]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wjYPC-0000000BHvm-0zJO for linux-amlogic@lists.infradead.org; Tue, 14 Jul 2026 08:22:18 +0000 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by tor.source.kernel.org (Postfix) with ESMTP id 3BB7A60120; Tue, 14 Jul 2026 08:22:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6F34A1F000E9; Tue, 14 Jul 2026 08:22:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784017336; bh=ZgCfN1XdYNEEHbdhzLqMbv1I7M4zFQsvLNwz9yYNGV0=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=IaJwc/2ec84qLtUX4arFfxSKhYY5gWM3olvcuIYy/3/J8ck3H5/ugafBDRIStsr7j ewN2X0MoB1DlzCx5pqBwBR634gBWvlkwqTBxp2jl0Ka/8NXVAi2++GdQ/0WlrMZp9F zrn4gtuxYxORYuh/hN8L2wQ7+AmZ7i2SeTFokCMjksTSv7fy1nYlUhXfPk77rdOjXC hYGZ8De+Ef11i9m4tzyjNkLJW0+5i72CwjUP6FbMJvLx9gCslYvg5lRka1q48zdIjX 8HWBvR6cX/9LGbD/1QfeQ+szNY5qf/fupoH7g+0It4kxAs6lv0EeFqibPMfUltnn8a YEajG60lit0Cg== From: sashiko-bot@kernel.org Subject: Re: [PATCH v11 2/3] dmaengine: amlogic: Add general DMA driver for A9 To: "Xianwei Zhao" Cc: devicetree@vger.kernel.org, dmaengine@vger.kernel.org, Frank.Li@kernel.org, vkoul@kernel.org, robh@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, linux-amlogic@lists.infradead.org In-Reply-To: <20260714-amlogic-dma-v11-2-de79c2394282@amlogic.com> References: <20260714-amlogic-dma-v11-0-de79c2394282@amlogic.com> <20260714-amlogic-dma-v11-2-de79c2394282@amlogic.com> Date: Tue, 14 Jul 2026 08:22:15 +0000 Message-Id: <20260714082216.6F34A1F000E9@smtp.kernel.org> X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: sashiko-reviews@lists.linux.dev MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org VGhhbmsgeW91IGZvciB5b3VyIGNvbnRyaWJ1dGlvbiEgU2FzaGlrbyBBSSByZXZpZXcgZm91bmQg NyBwb3RlbnRpYWwgaXNzdWUocykgdG8gY29uc2lkZXI6Ci0gW0hpZ2hdIGFtbF9kbWFfdHhfc3Rh dHVzIGZhbHNlbHkgcmVwb3J0cyBpbi1mbGlnaHQgdHJhbnNmZXJzIGFzIERNQV9DT01QTEVURSwg Y2F1c2luZyBkYXRhIGNvcnJ1cHRpb24uCi0gW0hpZ2hdIERhdGEgcmFjZSBhbmQgVE9DVE9VIE5V TEwgcG9pbnRlciBkZXJlZmVyZW5jZSBpbiBhbWxfZG1hX3R4X3N0YXR1cyBkdWUgdG8gZWFybHkg bG9jayByZWxlYXNlLgotIFtIaWdoXSBVc2UtQWZ0ZXItRnJlZSBpbiBkZXZyZXMtbWFuYWdlZCBy ZW1vdmUgcGF0aCBkdWUgdG8gdGFza2xldCBzY2hlZHVsZWQgYWZ0ZXIgdGFza2xldF9raWxsLgot IFtIaWdoXSBQZW5kaW5nIGZyZWVfd29yayBpdGVtcyBvbiB0aGUgZ2xvYmFsIHdvcmtxdWV1ZSBj YXVzZSBhIGtlcm5lbCBwYW5pYyBvbiBtb2R1bGUgdW5sb2FkLgotIFtIaWdoXSBhbWxfZG1hX3Rl cm1pbmF0ZV9hbGwoKSBtYXNrcyBpbnRlcnJ1cHRzIGJ1dCBkb2VzIG5vdCBjbGVhciBwZW5kaW5n IGludGVycnVwdCBzdGF0dXMsIHBvdGVudGlhbGx5IGNvcnJ1cHRpbmcgc3Vic2VxdWVudCB0cmFu c2ZlcnMuCi0gW01lZGl1bV0gTWlzc2luZyBzcmNfYWRkcl93aWR0aHMgY29uZmlndXJhdGlvbiBw cmV2ZW50cyBETUFfREVWX1RPX01FTSBjbGllbnRzIGZyb20gdmFsaWRhdGluZyBjYXBhYmlsaXRp ZXMuCi0gW01lZGl1bV0gRE1BIGRlc2NyaXB0b3JzIHVzZSBob3N0LWVuZGlhbiBmaWVsZHMsIGJy ZWFraW5nIGhhcmR3YXJlIGZ1bmN0aW9uYWxpdHkgb24gYmlnLWVuZGlhbiBwbGF0Zm9ybXMuCi0t CgotLS0gUGF0Y2ggWzJdOiBbUEFUQ0ggdjExIDIvM10gZG1hZW5naW5lOiBhbWxvZ2ljOiBBZGQg Z2VuZXJhbCBETUEgZHJpdmVyIGZvciBBOSAtLS0KY29tbWl0IDkxZDRjOWMwOWU5YjNiYWEwOTMx ZGFlMWUzN2MwMjJmYWUyYjc0NDcKQXV0aG9yOiBYaWFud2VpIFpoYW8gPHhpYW53ZWkuemhhb0Bh bWxvZ2ljLmNvbT4KCmRtYWVuZ2luZTogYW1sb2dpYzogQWRkIGdlbmVyYWwgRE1BIGRyaXZlciBm b3IgQTkKClRoaXMgcGF0Y2ggaW50cm9kdWNlcyBhIG5ldyBETUEgZW5naW5lIGRyaXZlciBmb3Ig QW1sb2dpYyBBOSBTb0NzLiBUaGUKZ2VuZXJhbC1wdXJwb3NlIERNQSBjb250cm9sbGVyIGlzIHVz ZWQgYnkgbXVsdGlwbGUgcGVyaXBoZXJhbHMgc3VjaCBhcyBJMkMsClBJTywgYW5kIEkzQy4KCj4g ZGlmZiAtLWdpdCBhL2RyaXZlcnMvZG1hL2FtbG9naWMtZG1hLmMgYi9kcml2ZXJzL2RtYS9hbWxv Z2ljLWRtYS5jCj4gbmV3IGZpbGUgbW9kZSAxMDA2NDQKPiBpbmRleCAwMDAwMDAwMDAwMDAwLi45 ZGU2NTBhNzlhYmFjCj4gLS0tIC9kZXYvbnVsbAo+ICsrKyBiL2RyaXZlcnMvZG1hL2FtbG9naWMt ZG1hLmMKClsgLi4uIF0KCj4gK3N0cnVjdCBhbWxfZG1hX3NnX2xpbmsgewo+ICsjZGVmaW5lIExJ TktfTEVOCQlHRU5NQVNLKDI2LCAwKQo+ICsjZGVmaW5lIExJTktfSVJRCQlCSVQoMjcpCj4gKyNk ZWZpbmUgTElOS19FT0MJCUJJVCgyOCkKPiArI2RlZmluZSBMSU5LX0xPT1AJCUJJVCgyOSkKPiAr I2RlZmluZSBMSU5LX0VSUgkJQklUKDMwKQo+ICsjZGVmaW5lIExJTktfT1dORVIJCUJJVCgzMSkK PiArCXUzMiBjdGw7Cj4gKwl1MzIgYWRkcl9sb3c7Cj4gKwl1MzIgYWRkcl9oaWdoOwo+ICsJdTMy IHJldmVyZWQ7Cj4gK30gX19wYWNrZWQ7CgpbU2V2ZXJpdHk6IE1lZGl1bV0KU2luY2UgdGhpcyBz dHJ1Y3R1cmUgZGVzY3JpYmVzIGEgaGFyZHdhcmUgbWVtb3J5IGRlc2NyaXB0b3IsIHNob3VsZCB0 aGVzZQpmaWVsZHMgdXNlIF9fbGUzMiBpbnN0ZWFkIG9mIHUzMiB0byBlbnN1cmUgdGhlIGRyaXZl ciBmdW5jdGlvbnMgY29ycmVjdGx5IG9uCmJpZy1lbmRpYW4gYXJjaGl0ZWN0dXJlcz8KClsgLi4u IF0KCj4gK3N0YXRpYyB2b2lkIGFtbF9kbWFfZnJlZV9kZXNjKHN0cnVjdCB2aXJ0X2RtYV9kZXNj ICp2ZCkKPiArewo+ICsJc3RydWN0IGFtbF9kbWFfZGVzYyAqYW1sX2Rlc2MgPSB0b19hbWxfZG1h X2Rlc2ModmQpOwo+ICsKPiArCXNjaGVkdWxlX3dvcmsoJmFtbF9kZXNjLT5mcmVlX3dvcmspOwo+ ICt9CgpbU2V2ZXJpdHk6IEhpZ2hdCkRvZXMgc2NoZWR1bGluZyBtZW1vcnkgY2xlYW51cCBvbiB0 aGUgc3lzdGVtIHdvcmtxdWV1ZSBoZXJlIGludHJvZHVjZSBhIHBhbmljCm9uIG1vZHVsZSB1bmxv YWQ/CgpJZiB0aGUgZHJpdmVyIG1vZHVsZSBpcyB1bmxvYWRlZCB3aGlsZSBhIHdvcmsgaXRlbSBp cyBzdGlsbCBwZW5kaW5nLCB0aGUKbW9kdWxlJ3MgdGV4dCBzZWdtZW50IHdpbGwgYmUgdW5tYXBw ZWQuIFdoZW4gdGhlIHdvcmtxdWV1ZSBleGVjdXRlcwphbWxfZG1hX2ZyZWVfZGVzY193b3JrKCks IGl0IG1pZ2h0IGp1bXAgdG8gdW5tYXBwZWQgbWVtb3J5IGJlY2F1c2UKYW1sX2RtYV9yZW1vdmUo KSBkb2VzIG5vdCBhcHBlYXIgdG8gZmx1c2ggdGhpcyB3b3JrLgoKWyAuLi4gXQoKPiArc3RhdGlj IGVudW0gZG1hX3N0YXR1cyBhbWxfZG1hX3R4X3N0YXR1cyhzdHJ1Y3QgZG1hX2NoYW4gKmNoYW4s Cj4gKwkJCQkJIGRtYV9jb29raWVfdCBjb29raWUsCj4gKwkJCQkJIHN0cnVjdCBkbWFfdHhfc3Rh dGUgKnR4c3RhdGUpCj4gK3sKPiArCXN0cnVjdCBhbWxfZG1hX2NoYW4gKmFtbF9jaGFuID0gdG9f YW1sX2RtYV9jaGFuKGNoYW4pOwo+ICsJc3RydWN0IGFtbF9kbWFfZGV2ICphbWxfZG1hID0gYW1s X2NoYW4tPmFtbF9kbWE7Cj4gKwlzdHJ1Y3QgYW1sX2RtYV9kZXNjICphbWxfZGVzYyA9IE5VTEw7 Cj4gKwlzdHJ1Y3QgdmlydF9kbWFfZGVzYyAqdmQ7Cj4gKwl1MzIgcmVzaWR1ZSA9IDAsIGRvbmU7 Cj4gKwl1bnNpZ25lZCBsb25nIGZsYWdzOwo+ICsJZW51bSBkbWFfc3RhdHVzIHJldDsKPiArCj4g KwlyZXQgPSBkbWFfY29va2llX3N0YXR1cyhjaGFuLCBjb29raWUsIHR4c3RhdGUpOwo+ICsJaWYg KHJldCA9PSBETUFfQ09NUExFVEUpCj4gKwkJcmV0dXJuIHJldDsKPiArCj4gKwlyZXQgPSBhbWxf Y2hhbi0+c3RhdHVzOwoKW1NldmVyaXR5OiBIaWdoXQpDb3VsZCB0aGlzIG92ZXJ3cml0ZSB0aGUg Y29ycmVjdCBETUFfSU5fUFJPR1JFU1MgcmV0dXJuIHZhbHVlIGZyb20KZG1hX2Nvb2tpZV9zdGF0 dXMoKSB3aXRoIGFtbF9jaGFuLT5zdGF0dXM/CgpJZiBhbWxfY2hhbi0+c3RhdHVzIGlzIHVzdWFs bHkgc2V0IHRvIERNQV9DT01QTEVURSBkdXJpbmcgaW5pdGlhbGl6YXRpb24sCnBvbGxpbmcgY2xp ZW50cyBtaWdodCBtaXN0YWtlbmx5IGJlbGlldmUgdGhlIHRyYW5zZmVyIGlzIGZpbmlzaGVkIGJl Zm9yZSBpdAphY3R1YWxseSBpcywgbGVhZGluZyB0byBkYXRhIGNvcnJ1cHRpb24uCgo+ICsJaWYg KCF0eHN0YXRlKQo+ICsJCXJldHVybiByZXQ7Cj4gKwo+ICsJc3Bpbl9sb2NrX2lycXNhdmUoJmFt bF9jaGFuLT52Y2hhbi5sb2NrLCBmbGFncyk7Cj4gKwl2ZCA9IHZjaGFuX2ZpbmRfZGVzYygmYW1s X2NoYW4tPnZjaGFuLCBjb29raWUpOwo+ICsJc3Bpbl91bmxvY2tfaXJxcmVzdG9yZSgmYW1sX2No YW4tPnZjaGFuLmxvY2ssIGZsYWdzKTsKPiArCWlmICh2ZCkgewo+ICsJCWFtbF9kZXNjID0gdG9f YW1sX2RtYV9kZXNjKHZkKTsKPiArCQlyZXNpZHVlID0gYW1sX2Rlc2MtPmRhdGFfbGVuOwo+ICsJ fSBlbHNlIGlmIChhbWxfY2hhbi0+Y3VyX2Rlc2MgJiYgYW1sX2NoYW4tPmN1cl9kZXNjLT52ZC50 eC5jb29raWUgPT0gY29va2llKSB7CgpbU2V2ZXJpdHk6IEhpZ2hdCkNhbiByZWxlYXNpbmcgdGhl IGxvY2sgYmVmb3JlIGFjY2Vzc2luZyBhbWxfY2hhbi0+Y3VyX2Rlc2MgbGVhZCB0byBhCk5VTEwg cG9pbnRlciBkZXJlZmVyZW5jZT8KCklmIGEgaGFyZHdhcmUgaW50ZXJydXB0IGNvbXBsZXRlcyB0 aGUgdHJhbnNmZXIgY29uY3VycmVudGx5LCBpdCBzZXRzIGN1cl9kZXNjCnRvIE5VTEwuIEEgdGhy ZWFkIGV4ZWN1dGluZyB0aGlzIGNvZGUgY291bGQgY2hlY2sgYW1sX2NoYW4tPmN1cl9kZXNjIChm aW5kaW5nCml0IG5vbi1OVUxMKSwgYnV0IGlmIHRoZSBpbnRlcnJ1cHQgaGFuZGxlciBjbGVhcnMg dGhlIHBvaW50ZXIgcmlnaHQgYWZ0ZXIsCnRoZSBzdWJzZXF1ZW50IGFtbF9jaGFuLT5jdXJfZGVz Yy0+dmQudHguY29va2llIGFjY2VzcyB3b3VsZCBkZXJlZmVyZW5jZSBOVUxMLgoKQWx0ZXJuYXRp dmVseSwgYW1sX2Rlc2MgY291bGQgYmUgYXNzaWduZWQgTlVMTCwgY2F1c2luZyBhIGRlcmVmZXJl bmNlIHdoZW4KY2FsY3VsYXRpbmcgdGhlIHJlc2lkdWUuCgo+ICsJCWFtbF9kZXNjID0gYW1sX2No YW4tPmN1cl9kZXNjOwo+ICsJCXJlZ21hcF9yZWFkKGFtbF9kbWEtPnJlZ21hcCwgYW1sX2NoYW4t PnJlZ19vZmZzICsgUkNIX1JEX0xFTiwgJmRvbmUpOwo+ICsJCXJlc2lkdWUgPSBhbWxfZGVzYy0+ ZGF0YV9sZW4gLSBkb25lOwo+ICsJfSBlbHNlIHsKPiArCQlkZXZfZXJyKGFtbF9kbWEtPmRtYV9k ZXZpY2UuZGV2LCAiY29va2llIGVycm9yXG4iKTsKPiArCX0KPiArCWRtYV9zZXRfcmVzaWR1ZSh0 eHN0YXRlLCByZXNpZHVlKTsKPiArCj4gKwlyZXR1cm4gcmV0Owo+ICt9CgpbIC4uLiBdCgo+ICtz dGF0aWMgc3RydWN0IGRtYV9hc3luY190eF9kZXNjcmlwdG9yICphbWxfZG1hX3ByZXBfc2xhdmVf c2cKPiArCQkoc3RydWN0IGRtYV9jaGFuICpjaGFuLCBzdHJ1Y3Qgc2NhdHRlcmxpc3QgKnNnbCwK PiArCQl1bnNpZ25lZCBpbnQgc2dfbGVuLCBlbnVtIGRtYV90cmFuc2Zlcl9kaXJlY3Rpb24gZGly ZWN0aW9uLAo+ICsJCXVuc2lnbmVkIGxvbmcgZmxhZ3MsIHZvaWQgKmNvbnRleHQpCj4gK3sKClsg Li4uIF0KCj4gKwkJd2hpbGUgKGF2YWlsID4gU0dfTUFYX0xFTikgewo+ICsJCQkvKiBzZXQgZG1h IGFkZHJlc3MgYW5kIGxlbiB0byBzZ2xpbmsqLwo+ICsJCQlzZ19saW5rLT5hZGRyX2xvdyA9IGxv d2VyXzMyX2JpdHMocGFkZHIpOwo+ICsJCQlzZ19saW5rLT5hZGRyX2hpZ2ggPSB1cHBlcl8zMl9i aXRzKHBhZGRyKTsKPiArCQkJc2dfbGluay0+Y3RsID0gRklFTERfUFJFUChMSU5LX0xFTiwgU0df TUFYX0xFTik7CgpbU2V2ZXJpdHk6IE1lZGl1bV0KU2hvdWxkIHRoZXNlIGFzc2lnbm1lbnRzIHVz ZSBjcHVfdG9fbGUzMigpIHRvIGVuc3VyZSBwcm9wZXIgY29udmVyc2lvbiBvZgpob3N0LWVuZGlh biB2YWx1ZXMgYmVmb3JlIHdyaXRpbmcgdG8gY29oZXJlbnQgRE1BIG1lbW9yeT8gV2l0aG91dCBp dCwgdGhpcwpjb3VsZCBicmVhayBoYXJkd2FyZSBmdW5jdGlvbmFsaXR5IG9uIGJpZy1lbmRpYW4g cGxhdGZvcm1zLgoKWyAuLi4gXQoKPiArc3RhdGljIGludCBhbWxfZG1hX3Rlcm1pbmF0ZV9hbGwo c3RydWN0IGRtYV9jaGFuICpjaGFuKQo+ICt7CgpbIC4uLiBdCgo+ICsJc3Bpbl9sb2NrX2lycXNh dmUoJmFtbF9jaGFuLT52Y2hhbi5sb2NrLCBmbGFncyk7Cj4gKwlyZWdtYXBfc2V0X2JpdHMoYW1s X2RtYS0+cmVnbWFwLCBhbWxfY2hhbi0+cmVnX29mZnMgKyBSQ0hfQ0ZHLCBDRkdfUEFVU0UpOwo+ ICsJcmVnbWFwX3NldF9iaXRzKGFtbF9kbWEtPnJlZ21hcCwgYW1sX2NoYW4tPnJlZ19vZmZzICsg UkNIX0NGRywgQ0ZHX0NMRUFSKTsKPiArCj4gKwlpZiAoYW1sX2NoYW4tPmRpcmVjdGlvbiA9PSBE TUFfTUVNX1RPX0RFVikKPiArCQlyZWdtYXBfc2V0X2JpdHMoYW1sX2RtYS0+cmVnbWFwLCBSQ0hf SU5UX01BU0ssIEJJVChjaGFuX2lkKSk7Cj4gKwllbHNlIGlmIChhbWxfY2hhbi0+ZGlyZWN0aW9u ID09IERNQV9ERVZfVE9fTUVNKQo+ICsJCXJlZ21hcF9zZXRfYml0cyhhbWxfZG1hLT5yZWdtYXAs IFdDSF9JTlRfTUFTSywgQklUKGNoYW5faWQpKTsKCltTZXZlcml0eTogSGlnaF0KRG9lcyBtYXNr aW5nIHRoZSBpbnRlcnJ1cHRzIGhlcmUgd2l0aG91dCBhbHNvIGNsZWFyaW5nIHRoZSBwZW5kaW5n IGludGVycnVwdApzdGF0dXMgKHZpYSBDTEVBUl9SQ0ggb3IgQ0xFQVJfV0NIKSByaXNrIGNvcnJ1 cHRpbmcgc3Vic2VxdWVudCB0cmFuc2ZlcnM/CgpJZiBhbiBpbnRlcnJ1cHQgaXMgYWxyZWFkeSBw ZW5kaW5nLCBpdHMgc3RhdHVzIGJpdCByZW1haW5zIHNldC4gV2hlbgphbWxfZG1hX3N0YXJ0KCkg aXMgY2FsbGVkIGxhdGVyIGFuZCB1bm1hc2tzIHRoZSBpbnRlcnJ1cHQsIGl0IHdpbGwgZmlyZQpp bW1lZGlhdGVseSBhbmQgZmFsc2VseSBjb21wbGV0ZSB0aGUgbmV3IHRyYW5zZmVyLgoKWyAuLi4g XQoKPiArc3RhdGljIGludCBhbWxfZG1hX3Byb2JlKHN0cnVjdCBwbGF0Zm9ybV9kZXZpY2UgKnBk ZXYpCj4gK3sKClsgLi4uIF0KCj4gKwlkbWFfZGV2LT5kZXZpY2VfaXNzdWVfcGVuZGluZyA9IGFt bF9kbWFfaXNzdWVfcGVuZGluZzsKPiArCS8qIFBJTyA0IGJ5dGVzIGFuZCBJMkMgMSBieXRlICov Cj4gKwlkbWFfZGV2LT5kc3RfYWRkcl93aWR0aHMgPSBCSVQoRE1BX1NMQVZFX0JVU1dJRFRIXzRf QllURVMpIHwgQklUKERNQV9TTEFWRV9CVVNXSURUSF8xX0JZVEUpOwo+ICsJZG1hX2Rldi0+ZGly ZWN0aW9ucyA9IEJJVChETUFfREVWX1RPX01FTSkgfCBCSVQoRE1BX01FTV9UT19ERVYpOwoKW1Nl dmVyaXR5OiBNZWRpdW1dClNpbmNlIHRoaXMgZHJpdmVyIGFkdmVydGlzZXMgRE1BX0RFVl9UT19N RU0gc3VwcG9ydCwgaXMgdGhlcmUgYSBtaXNzaW5nCmNvbmZpZ3VyYXRpb24gZm9yIHNyY19hZGRy X3dpZHRocz8KCklmIG9taXR0ZWQsIGNsaWVudCBkcml2ZXJzIHZhbGlkYXRpbmcgc291cmNlIHdp ZHRocyB1c2luZwpkbWFfZ2V0X3NsYXZlX2NhcHMoKSB3aWxsIHNlZSBhIHdpZHRoIG9mIDAgYW5k IG1pZ2h0IGZhaWwgaW5pdGlhbGl6YXRpb24uCgpbIC4uLiBdCgo+ICtzdGF0aWMgdm9pZCBhbWxf ZG1hX3JlbW92ZShzdHJ1Y3QgcGxhdGZvcm1fZGV2aWNlICpwZGV2KQo+ICt7Cj4gKwlzdHJ1Y3Qg YW1sX2RtYV9kZXYgKmFtbF9kbWEgPSBwbGF0Zm9ybV9nZXRfZHJ2ZGF0YShwZGV2KTsKPiArCXN0 cnVjdCBhbWxfZG1hX2NoYW4gKmFtbF9jaGFuID0gTlVMTDsKPiArCWludCBpOwo+ICsKPiArCW9m X2RtYV9jb250cm9sbGVyX2ZyZWUoKCZwZGV2LT5kZXYpLT5vZl9ub2RlKTsKPiArCj4gKwlyZWdt YXBfd3JpdGUoYW1sX2RtYS0+cmVnbWFwLCBSQ0hfSU5UX01BU0ssIDB4ZmZmZmZmZmYpOwo+ICsJ cmVnbWFwX3dyaXRlKGFtbF9kbWEtPnJlZ21hcCwgV0NIX0lOVF9NQVNLLCAweGZmZmZmZmZmKTsK PiArCj4gKwlmb3IgKGkgPSAwOyBpIDwgTUFYX0NIQU5fSUQ7IGkrKykgewo+ICsJCWFtbF9jaGFu ID0gYW1sX2RtYS0+YW1sX3JjaFtpXTsKPiArCQlpZiAoYW1sX2NoYW4pCj4gKwkJCXRhc2tsZXRf a2lsbCgmYW1sX2NoYW4tPnZjaGFuLnRhc2spOwo+ICsJCWFtbF9jaGFuID0gYW1sX2RtYS0+YW1s X3djaFtpXTsKPiArCQlpZiAoYW1sX2NoYW4pCj4gKwkJCXRhc2tsZXRfa2lsbCgmYW1sX2NoYW4t PnZjaGFuLnRhc2spOwo+ICsJfQo+ICt9CgpbU2V2ZXJpdHk6IEhpZ2hdCkNhbiBhIHVzZS1hZnRl ci1mcmVlIG9jY3VyIGR1cmluZyBkcml2ZXIgdW5iaW5kIGlmIGFuIGludGVycnVwdCBmaXJlcwpj b25jdXJyZW50bHk/CgpTaW5jZSB0aGUgZGV2cmVzLW1hbmFnZWQgSVJRIGlzIG5vdCBmcmVlZCBv ciBzeW5jaHJvbml6ZWQgYmVmb3JlIGNhbGxpbmcKdGFza2xldF9raWxsKCksIGFuIGFjdGl2ZSBp bnRlcnJ1cHQgaGFuZGxlciBvbiBhbm90aGVyIENQVSBjb3VsZCBzY2hlZHVsZSB0aGUKdGFza2xl dCBhZ2FpbiByaWdodCBhZnRlciB0YXNrbGV0X2tpbGwoKSByZXR1cm5zLiBPbmNlIHRoZSByZW1v dmUgZnVuY3Rpb24KZmluaXNoZXMsIGRldnJlcyBmcmVlcyB0aGUgY2hhbm5lbCBtZW1vcnkgY29u dGFpbmluZyB0aGUgdGFza2xldCwgbGVhZGluZyB0bwpleGVjdXRpb24gb24gZnJlZWQgbWVtb3J5 LgoKLS0gClNhc2hpa28gQUkgcmV2aWV3IMK3IGh0dHBzOi8vc2FzaGlrby5kZXYvIy9wYXRjaHNl dC8yMDI2MDcxNC1hbWxvZ2ljLWRtYS12MTEtMC1kZTc5YzIzOTQyODJAYW1sb2dpYy5jb20/cGFy dD0yCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51 eC1hbWxvZ2ljIG1haWxpbmcgbGlzdApsaW51eC1hbWxvZ2ljQGxpc3RzLmluZnJhZGVhZC5vcmcK aHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1hbWxvZ2lj Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A99713FBED8; Tue, 14 Jul 2026 08:22:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784017348; cv=none; b=D8J3vRglrQ2LDhkr1isZlevJryQfscy78RFgZXx5pTrGCdt6l4IMjhVCm9xqJbWtje9gPsj/t12EXsvLiQLYk9l1JfyBQHjvq7e9oAZR5WIG3qFcqWq1DfAHrWuPzKIFNTfEXNLZDH4iyyr2s8a3bLEEXkXyZMRAtZp18mOweLM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784017348; c=relaxed/simple; bh=2wmllSFtRM04qkBx6rOyomFUoGUsSeG5w4KKjMQgOus=; h=From:Subject:To:Cc:In-Reply-To:References:Content-Type:Date: Message-Id; b=m0NeUz1ezgWfwXn6SYXnX80d0Q0iT9kAHKlvNY6XUi3CYHHQcCxtedRM6jZ8j3WYskfTB0cjzWZAz8lVw/cqXgg7xDI5iPTGJ9qi3B1tSaCJFaKRhevnNXMGP8bzi2xBjC1WsqDFXZntcTDp0k6dFy9YU5lD1Fc7PTkStC04jK4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=IaJwc/2e; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IaJwc/2e" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6F34A1F000E9; Tue, 14 Jul 2026 08:22:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784017336; bh=ZgCfN1XdYNEEHbdhzLqMbv1I7M4zFQsvLNwz9yYNGV0=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=IaJwc/2ec84qLtUX4arFfxSKhYY5gWM3olvcuIYy/3/J8ck3H5/ugafBDRIStsr7j ewN2X0MoB1DlzCx5pqBwBR634gBWvlkwqTBxp2jl0Ka/8NXVAi2++GdQ/0WlrMZp9F zrn4gtuxYxORYuh/hN8L2wQ7+AmZ7i2SeTFokCMjksTSv7fy1nYlUhXfPk77rdOjXC hYGZ8De+Ef11i9m4tzyjNkLJW0+5i72CwjUP6FbMJvLx9gCslYvg5lRka1q48zdIjX 8HWBvR6cX/9LGbD/1QfeQ+szNY5qf/fupoH7g+0It4kxAs6lv0EeFqibPMfUltnn8a YEajG60lit0Cg== From: sashiko-bot@kernel.org Subject: Re: [PATCH v11 2/3] dmaengine: amlogic: Add general DMA driver for A9 Reply-To: sashiko-reviews@lists.linux.dev To: "Xianwei Zhao" Cc: devicetree@vger.kernel.org, dmaengine@vger.kernel.org, Frank.Li@kernel.org, vkoul@kernel.org, robh@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, linux-amlogic@lists.infradead.org In-Reply-To: <20260714-amlogic-dma-v11-2-de79c2394282@amlogic.com> References: <20260714-amlogic-dma-v11-0-de79c2394282@amlogic.com> <20260714-amlogic-dma-v11-2-de79c2394282@amlogic.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Tue, 14 Jul 2026 08:22:15 +0000 Message-Id: <20260714082216.6F34A1F000E9@smtp.kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Thank you for your contribution! Sashiko AI review found 7 potential issue(= s) to consider: - [High] aml_dma_tx_status falsely reports in-flight transfers as DMA_COMPL= ETE, causing data corruption. - [High] Data race and TOCTOU NULL pointer dereference in aml_dma_tx_status= due to early lock release. - [High] Use-After-Free in devres-managed remove path due to tasklet schedu= led after tasklet_kill. - [High] Pending free_work items on the global workqueue cause a kernel pan= ic on module unload. - [High] aml_dma_terminate_all() masks interrupts but does not clear pendin= g interrupt status, potentially corrupting subsequent transfers. - [Medium] Missing src_addr_widths configuration prevents DMA_DEV_TO_MEM cl= ients from validating capabilities. - [Medium] DMA descriptors use host-endian fields, breaking hardware functi= onality on big-endian platforms. -- --- Patch [2]: [PATCH v11 2/3] dmaengine: amlogic: Add general DMA driver f= or A9 --- commit 91d4c9c09e9b3baa0931dae1e37c022fae2b7447 Author: Xianwei Zhao dmaengine: amlogic: Add general DMA driver for A9 This patch introduces a new DMA engine driver for Amlogic A9 SoCs. The general-purpose DMA controller is used by multiple peripherals such as I2C, PIO, and I3C. > diff --git a/drivers/dma/amlogic-dma.c b/drivers/dma/amlogic-dma.c > new file mode 100644 > index 0000000000000..9de650a79abac > --- /dev/null > +++ b/drivers/dma/amlogic-dma.c [ ... ] > +struct aml_dma_sg_link { > +#define LINK_LEN GENMASK(26, 0) > +#define LINK_IRQ BIT(27) > +#define LINK_EOC BIT(28) > +#define LINK_LOOP BIT(29) > +#define LINK_ERR BIT(30) > +#define LINK_OWNER BIT(31) > + u32 ctl; > + u32 addr_low; > + u32 addr_high; > + u32 revered; > +} __packed; [Severity: Medium] Since this structure describes a hardware memory descriptor, should these fields use __le32 instead of u32 to ensure the driver functions correctly on big-endian architectures? [ ... ] > +static void aml_dma_free_desc(struct virt_dma_desc *vd) > +{ > + struct aml_dma_desc *aml_desc =3D to_aml_dma_desc(vd); > + > + schedule_work(&aml_desc->free_work); > +} [Severity: High] Does scheduling memory cleanup on the system workqueue here introduce a pan= ic on module unload? If the driver module is unloaded while a work item is still pending, the module's text segment will be unmapped. When the workqueue executes aml_dma_free_desc_work(), it might jump to unmapped memory because aml_dma_remove() does not appear to flush this work. [ ... ] > +static enum dma_status aml_dma_tx_status(struct dma_chan *chan, > + dma_cookie_t cookie, > + struct dma_tx_state *txstate) > +{ > + struct aml_dma_chan *aml_chan =3D to_aml_dma_chan(chan); > + struct aml_dma_dev *aml_dma =3D aml_chan->aml_dma; > + struct aml_dma_desc *aml_desc =3D NULL; > + struct virt_dma_desc *vd; > + u32 residue =3D 0, done; > + unsigned long flags; > + enum dma_status ret; > + > + ret =3D dma_cookie_status(chan, cookie, txstate); > + if (ret =3D=3D DMA_COMPLETE) > + return ret; > + > + ret =3D aml_chan->status; [Severity: High] Could this overwrite the correct DMA_IN_PROGRESS return value from dma_cookie_status() with aml_chan->status? If aml_chan->status is usually set to DMA_COMPLETE during initialization, polling clients might mistakenly believe the transfer is finished before it actually is, leading to data corruption. > + if (!txstate) > + return ret; > + > + spin_lock_irqsave(&aml_chan->vchan.lock, flags); > + vd =3D vchan_find_desc(&aml_chan->vchan, cookie); > + spin_unlock_irqrestore(&aml_chan->vchan.lock, flags); > + if (vd) { > + aml_desc =3D to_aml_dma_desc(vd); > + residue =3D aml_desc->data_len; > + } else if (aml_chan->cur_desc && aml_chan->cur_desc->vd.tx.cookie =3D= =3D cookie) { [Severity: High] Can releasing the lock before accessing aml_chan->cur_desc lead to a NULL pointer dereference? If a hardware interrupt completes the transfer concurrently, it sets cur_de= sc to NULL. A thread executing this code could check aml_chan->cur_desc (findi= ng it non-NULL), but if the interrupt handler clears the pointer right after, the subsequent aml_chan->cur_desc->vd.tx.cookie access would dereference NU= LL. Alternatively, aml_desc could be assigned NULL, causing a dereference when calculating the residue. > + aml_desc =3D aml_chan->cur_desc; > + regmap_read(aml_dma->regmap, aml_chan->reg_offs + RCH_RD_LEN, &done); > + residue =3D aml_desc->data_len - done; > + } else { > + dev_err(aml_dma->dma_device.dev, "cookie error\n"); > + } > + dma_set_residue(txstate, residue); > + > + return ret; > +} [ ... ] > +static struct dma_async_tx_descriptor *aml_dma_prep_slave_sg > + (struct dma_chan *chan, struct scatterlist *sgl, > + unsigned int sg_len, enum dma_transfer_direction direction, > + unsigned long flags, void *context) > +{ [ ... ] > + while (avail > SG_MAX_LEN) { > + /* set dma address and len to sglink*/ > + sg_link->addr_low =3D lower_32_bits(paddr); > + sg_link->addr_high =3D upper_32_bits(paddr); > + sg_link->ctl =3D FIELD_PREP(LINK_LEN, SG_MAX_LEN); [Severity: Medium] Should these assignments use cpu_to_le32() to ensure proper conversion of host-endian values before writing to coherent DMA memory? Without it, this could break hardware functionality on big-endian platforms. [ ... ] > +static int aml_dma_terminate_all(struct dma_chan *chan) > +{ [ ... ] > + spin_lock_irqsave(&aml_chan->vchan.lock, flags); > + regmap_set_bits(aml_dma->regmap, aml_chan->reg_offs + RCH_CFG, CFG_PAUS= E); > + regmap_set_bits(aml_dma->regmap, aml_chan->reg_offs + RCH_CFG, CFG_CLEA= R); > + > + if (aml_chan->direction =3D=3D DMA_MEM_TO_DEV) > + regmap_set_bits(aml_dma->regmap, RCH_INT_MASK, BIT(chan_id)); > + else if (aml_chan->direction =3D=3D DMA_DEV_TO_MEM) > + regmap_set_bits(aml_dma->regmap, WCH_INT_MASK, BIT(chan_id)); [Severity: High] Does masking the interrupts here without also clearing the pending interrupt status (via CLEAR_RCH or CLEAR_WCH) risk corrupting subsequent transfers? If an interrupt is already pending, its status bit remains set. When aml_dma_start() is called later and unmasks the interrupt, it will fire immediately and falsely complete the new transfer. [ ... ] > +static int aml_dma_probe(struct platform_device *pdev) > +{ [ ... ] > + dma_dev->device_issue_pending =3D aml_dma_issue_pending; > + /* PIO 4 bytes and I2C 1 byte */ > + dma_dev->dst_addr_widths =3D BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | BIT(DMA_= SLAVE_BUSWIDTH_1_BYTE); > + dma_dev->directions =3D BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); [Severity: Medium] Since this driver advertises DMA_DEV_TO_MEM support, is there a missing configuration for src_addr_widths? If omitted, client drivers validating source widths using dma_get_slave_caps() will see a width of 0 and might fail initialization. [ ... ] > +static void aml_dma_remove(struct platform_device *pdev) > +{ > + struct aml_dma_dev *aml_dma =3D platform_get_drvdata(pdev); > + struct aml_dma_chan *aml_chan =3D NULL; > + int i; > + > + of_dma_controller_free((&pdev->dev)->of_node); > + > + regmap_write(aml_dma->regmap, RCH_INT_MASK, 0xffffffff); > + regmap_write(aml_dma->regmap, WCH_INT_MASK, 0xffffffff); > + > + for (i =3D 0; i < MAX_CHAN_ID; i++) { > + aml_chan =3D aml_dma->aml_rch[i]; > + if (aml_chan) > + tasklet_kill(&aml_chan->vchan.task); > + aml_chan =3D aml_dma->aml_wch[i]; > + if (aml_chan) > + tasklet_kill(&aml_chan->vchan.task); > + } > +} [Severity: High] Can a use-after-free occur during driver unbind if an interrupt fires concurrently? Since the devres-managed IRQ is not freed or synchronized before calling tasklet_kill(), an active interrupt handler on another CPU could schedule t= he tasklet again right after tasklet_kill() returns. Once the remove function finishes, devres frees the channel memory containing the tasklet, leading to execution on freed memory. --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20260714-amlogic-dm= a-v11-0-de79c2394282@amlogic.com?part=3D2