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Wed, 15 Jul 2026 03:33:36 +0000 From: Jamin Lin To: =?iso-8859-1?Q?Daniel_P=2E_Berrang=E9?= , =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Kane Chen , Andrew Jeffery , Joel Stanley , Eric Blake , Markus Armbruster , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: Jamin Lin , Troy Lee Subject: [PATCH v2 14/17] hw/misc/aspeed_hace: Support the AES-GCM mode for the crypto command Thread-Topic: [PATCH v2 14/17] hw/misc/aspeed_hace: Support the AES-GCM mode for the crypto command Thread-Index: AQHdFAq3ogjjqORDv0CAHW8aY++84g== Date: Wed, 15 Jul 2026 03:33:35 +0000 Message-ID: <20260715033311.1648424-15-jamin_lin@aspeedtech.com> References: <20260715033311.1648424-1-jamin_lin@aspeedtech.com> In-Reply-To: <20260715033311.1648424-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; 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envelope-from=jamin_lin@aspeedtech.com; helo=TYPPR03CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Implement the AES-GCM mode (HACE10[6:4] =3D 0b101) used by the AST2700=0A= crypto engine: decode the GCM selection, read the 96-bit IV from the=0A= context buffer, operate on the exact data length (GCM handles a partial=0A= final block itself), and write the 128-bit authentication tag to the tag=0A= buffer (HACE18/HACE8C). The hardware GCM path is only used without=0A= associated data (the driver falls back to software otherwise), so AAD is=0A= not modelled and a non-zero HACE14 is reported as unimplemented.=0A= =0A= Signed-off-by: Jamin Lin =0A= ---=0A= hw/misc/aspeed_hace.c | 70 ++++++++++++++++++++++++++++++++++++++-----=0A= 1 file changed, 62 insertions(+), 8 deletions(-)=0A= =0A= diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c=0A= index a807cc1422..927759b48f 100644=0A= --- a/hw/misc/aspeed_hace.c=0A= +++ b/hw/misc/aspeed_hace.c=0A= @@ -31,6 +31,9 @@=0A= /* HACE0C[27:0] holds the crypto data length */=0A= #define CRYPT_DATA_LEN_MASK 0x0FFFFFFF=0A= #define R_CRYPT_CMD (0x10 / 4)=0A= +/* AES-GCM associated data length (HACE14) and tag write buffer (HACE18) *= /=0A= +#define R_CRYPT_GCM_ADD_LEN (0x14 / 4)=0A= +#define R_CRYPT_GCM_TAG (0x18 / 4)=0A= /* Crypto engine command register (HACE10) bits */=0A= #define CRYPT_CMD_ENCRYPT BIT(7)=0A= #define CRYPT_CMD_ISR_EN BIT(12)=0A= @@ -43,6 +46,7 @@=0A= #define CRYPT_CMD_ECB (0x0 << 4)=0A= #define CRYPT_CMD_CBC (0x1 << 4)=0A= #define CRYPT_CMD_CTR (0x4 << 4)=0A= +#define CRYPT_CMD_GCM (0x5 << 4)=0A= /* AES key length HACE10[3:2] */=0A= #define CRYPT_CMD_AES_KEY_LEN_MASK (0x3 << 2)=0A= #define CRYPT_CMD_AES256 (0x2 << 2)=0A= @@ -58,10 +62,15 @@=0A= #define CRYPT_CTX_KEY_OFFSET 0x10=0A= #define CRYPT_CTX_SIZE 0x30=0A= =0A= +/* AES-GCM uses a 96-bit IV and a 128-bit authentication tag */=0A= +#define CRYPT_GCM_IV_LEN 12=0A= +#define CRYPT_GCM_TAG_LEN 16=0A= +=0A= /* AST2700 64-bit DMA high address registers for the crypto command */=0A= #define R_CRYPT_SRC_HI (0x80 / 4)=0A= #define R_CRYPT_DEST_HI (0x84 / 4)=0A= #define R_CRYPT_CONTEXT_HI (0x88 / 4)=0A= +#define R_CRYPT_GCM_TAG_HI (0x8c / 4)=0A= =0A= #define R_STATUS (0x1c / 4)=0A= #define HASH_IRQ BIT(9)=0A= @@ -598,6 +607,9 @@ static bool crypt_decode_cmd(uint32_t cmd, QCryptoCiphe= rAlgo *alg,=0A= case CRYPT_CMD_CTR:=0A= *mode =3D QCRYPTO_CIPHER_MODE_CTR;=0A= break;=0A= + case CRYPT_CMD_GCM:=0A= + *mode =3D QCRYPTO_CIPHER_MODE_GCM;=0A= + break;=0A= default:=0A= return false;=0A= }=0A= @@ -691,11 +703,12 @@ static uint64_t crypt_get_addr(AspeedHACEState *s, in= t reg, int reg_hi)=0A= }=0A= =0A= /*=0A= - * Perform an AES/DES/3DES ECB/CBC operation. The source and destination a= re=0A= - * either single contiguous buffers (direct access mode) or scatter-gather= =0A= - * lists (HACE10[18]/[19]), addressed by HACE00/HACE04; the IV/key come fr= om=0A= - * the context buffer (HACE08). For CBC the resulting chaining IV is writt= en=0A= - * back to the context buffer so the driver can continue the chain.=0A= + * Perform an AES/DES/3DES ECB/CBC/CTR or AES-GCM operation. The source an= d=0A= + * destination are either single contiguous buffers (direct access mode) o= r=0A= + * scatter-gather lists (HACE10[18]/[19]), addressed by HACE00/HACE04; the= =0A= + * IV/key come from the context buffer (HACE08). For CBC and CTR the resul= ting=0A= + * chaining state is written back to the context buffer so the driver can= =0A= + * continue; for GCM the authentication tag is written to the tag buffer.= =0A= */=0A= static void do_crypt_operation(AspeedHACEState *s, uint32_t cmd)=0A= {=0A= @@ -705,6 +718,7 @@ static void do_crypt_operation(AspeedHACEState *s, uint= 32_t cmd)=0A= g_autoptr(QCryptoCipher) cipher =3D NULL;=0A= g_autofree uint8_t *src_buf =3D NULL;=0A= g_autofree uint8_t *dst_buf =3D NULL;=0A= + uint8_t tag[CRYPT_GCM_TAG_LEN];=0A= uint8_t ctx[CRYPT_CTX_SIZE];=0A= Error *local_err =3D NULL;=0A= QCryptoCipherMode mode;=0A= @@ -713,10 +727,13 @@ static void do_crypt_operation(AspeedHACEState *s, ui= nt32_t cmd)=0A= uint64_t ctx_addr;=0A= uint64_t src_addr;=0A= uint64_t dst_addr;=0A= + uint64_t tag_addr;=0A= + uint32_t aad_len;=0A= size_t iv_offset;=0A= size_t blocklen;=0A= size_t buf_len;=0A= size_t keylen;=0A= + size_t ivlen;=0A= bool status;=0A= =0A= if (len =3D=3D 0) {=0A= @@ -736,6 +753,20 @@ static void do_crypt_operation(AspeedHACEState *s, uin= t32_t cmd)=0A= return;=0A= }=0A= =0A= + /* GCM uses a 96-bit IV; the block modes use a full-block IV. */=0A= + ivlen =3D (mode =3D=3D QCRYPTO_CIPHER_MODE_GCM) ? CRYPT_GCM_IV_LEN : b= locklen;=0A= +=0A= + /*=0A= + * The hardware GCM path is only exercised without associated data (th= e=0A= + * driver falls back to software when there is any), so AAD is not mod= elled.=0A= + */=0A= + aad_len =3D s->regs[R_CRYPT_GCM_ADD_LEN] & CRYPT_DATA_LEN_MASK;=0A= + if (mode =3D=3D QCRYPTO_CIPHER_MODE_GCM && aad_len !=3D 0) {=0A= + qemu_log_mask(LOG_UNIMP,=0A= + "%s: GCM associated data is not implemented\n", __fu= nc__);=0A= + return;=0A= + }=0A= +=0A= /* Fetch the IV and key from the context buffer in DRAM. */=0A= ctx_addr =3D crypt_get_addr(s, R_CRYPT_CONTEXT, R_CRYPT_CONTEXT_HI);= =0A= if (address_space_read(&s->dram_as, ctx_addr, MEMTXATTRS_UNSPECIFIED,= =0A= @@ -760,7 +791,7 @@ static void do_crypt_operation(AspeedHACEState *s, uint= 32_t cmd)=0A= }=0A= =0A= if (mode !=3D QCRYPTO_CIPHER_MODE_ECB &&=0A= - qcrypto_cipher_setiv(cipher, ctx + iv_offset, blocklen,=0A= + qcrypto_cipher_setiv(cipher, ctx + iv_offset, ivlen,=0A= &local_err) < 0) {=0A= qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto cipher setiv failed: %= s\n",=0A= __func__, error_get_pretty(local_err));=0A= @@ -771,9 +802,11 @@ static void do_crypt_operation(AspeedHACEState *s, uin= t32_t cmd)=0A= /*=0A= * Round the working buffers up to a whole block. Block modes are alre= ady=0A= * block-aligned; the stream-like CTR mode may leave a partial final b= lock=0A= - * that the engine still processes a full block at a time.=0A= + * that the engine still processes a full block at a time. GCM handles= a=0A= + * partial final block itself, so it operates on the exact length.=0A= */=0A= - buf_len =3D QEMU_ALIGN_UP(len, blocklen);=0A= + buf_len =3D (mode =3D=3D QCRYPTO_CIPHER_MODE_GCM) ?=0A= + len : QEMU_ALIGN_UP(len, blocklen);=0A= src_buf =3D g_malloc0(buf_len);=0A= dst_buf =3D g_malloc0(buf_len);=0A= =0A= @@ -857,6 +890,24 @@ static void do_crypt_operation(AspeedHACEState *s, uin= t32_t cmd)=0A= "%s: Failed to write IV, addr=3D0x%" HWADDR_PRIx= "\n",=0A= __func__, ctx_addr + iv_offset);=0A= }=0A= + } else if (mode =3D=3D QCRYPTO_CIPHER_MODE_GCM) {=0A= + /*=0A= + * GCM authenticates the message and writes the resulting tag to t= he=0A= + * dedicated tag buffer (HACE18/HACE8C).=0A= + */=0A= + if (qcrypto_cipher_gettag(cipher, tag, sizeof(tag), &local_err) < = 0) {=0A= + qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto cipher gettag fail= ed: "=0A= + "%s\n", __func__, error_get_pretty(local_err));= =0A= + error_free(local_err);=0A= + return;=0A= + }=0A= + tag_addr =3D crypt_get_addr(s, R_CRYPT_GCM_TAG, R_CRYPT_GCM_TAG_HI= );=0A= + if (address_space_write(&s->dram_as, tag_addr, MEMTXATTRS_UNSPECIF= IED,=0A= + tag, sizeof(tag))) {=0A= + qemu_log_mask(LOG_GUEST_ERROR,=0A= + "%s: Failed to write tag, addr=3D0x%" HWADDR_PRI= x "\n",=0A= + __func__, tag_addr);=0A= + }=0A= }=0A= }=0A= =0A= @@ -987,6 +1038,9 @@ static void aspeed_hace_write(void *opaque, hwaddr add= r, uint64_t data,=0A= case R_CRYPT_CONTEXT_HI:=0A= data &=3D ahc->key_hi_mask;=0A= break;=0A= + case R_CRYPT_GCM_TAG_HI:=0A= + data &=3D ahc->dest_hi_mask;=0A= + break;=0A= default:=0A= break;=0A= }=0A= -- =0A= 2.43.0=0A=