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Wed, 15 Jul 2026 03:33:18 +0000 From: Jamin Lin To: =?iso-8859-1?Q?Daniel_P=2E_Berrang=E9?= , =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Kane Chen , Andrew Jeffery , Joel Stanley , Eric Blake , Markus Armbruster , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: Jamin Lin , Troy Lee Subject: [PATCH v2 03/17] hw/misc/aspeed_hace: Support scatter-gather mode for the crypto command Thread-Topic: [PATCH v2 03/17] hw/misc/aspeed_hace: Support scatter-gather mode for the crypto command Thread-Index: AQHdFAqtgjMZaWWo4kmP72LwW7wHfg== Date: Wed, 15 Jul 2026 03:33:17 +0000 Message-ID: <20260715033311.1648424-4-jamin_lin@aspeedtech.com> References: <20260715033311.1648424-1-jamin_lin@aspeedtech.com> In-Reply-To: <20260715033311.1648424-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; 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envelope-from=jamin_lin@aspeedtech.com; helo=TYPPR03CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org The AST2600 and later crypto engines drive the source and destination=0A= through scatter-gather lists (HACE10[18]/[19]) rather than the single=0A= contiguous buffers used by the AST2500 direct access mode. Each SG list=0A= entry is a length word (SG_LIST_LEN_LAST marks the final entry) followed=0A= by a DRAM address, matching the hash engine layout.=0A= =0A= Add a crypt_prepare_sg() helper that gathers the source into / scatters=0A= the destination out of the bounce buffer by walking the SG list, and=0A= select it or the existing crypt_prepare_direct() from do_crypt_operation=0A= based on HACE10[18], mirroring the hash engine's direct/scatter-gather=0A= dispatch.=0A= =0A= Signed-off-by: Jamin Lin =0A= ---=0A= hw/misc/aspeed_hace.c | 70 +++++++++++++++++++++++++++++++++++++++----=0A= 1 file changed, 64 insertions(+), 6 deletions(-)=0A= =0A= diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c=0A= index de4399f322..3d3f1fc8dd 100644=0A= --- a/hw/misc/aspeed_hace.c=0A= +++ b/hw/misc/aspeed_hace.c=0A= @@ -610,13 +610,58 @@ static bool crypt_prepare_direct(AspeedHACEState *s, = uint64_t addr,=0A= }=0A= =0A= /*=0A= - * Perform an AES/DES/3DES ECB/CBC operation in direct access mode: the so= urce=0A= - * and destination are single contiguous buffers (HACE00/HACE04) and the I= V/key=0A= - * come from the context buffer (HACE08). For CBC the resulting chaining I= V is=0A= - * written back to the context buffer so the driver can continue the chain= .=0A= + * Scatter-gather mode: the source/destination register points at an SG li= st=0A= + * whose entries are a length word (SG_LIST_LEN_LAST flags the final entry= )=0A= + * followed by a DRAM address, matching the hash engine layout. Gather @le= n=0A= + * bytes into @buf, or scatter @buf back out when @to_dram is true.=0A= + * Returns true on success.=0A= + */=0A= +static bool crypt_prepare_sg(AspeedHACEState *s, uint64_t addr,=0A= + uint8_t *buf, uint32_t len, bool to_dram)=0A= +{=0A= + uint32_t copied =3D 0;=0A= + uint32_t sg_addr;=0A= + uint32_t sg_len;=0A= + uint32_t entry;=0A= + int i;=0A= +=0A= + for (i =3D 0; i < ASPEED_HACE_MAX_SG && copied < len; i++) {=0A= + entry =3D address_space_ldl_le(&s->dram_as, addr,=0A= + MEMTXATTRS_UNSPECIFIED, NULL);=0A= + sg_addr =3D address_space_ldl_le(&s->dram_as, addr + SG_LIST_LEN_S= IZE,=0A= + MEMTXATTRS_UNSPECIFIED, NULL);=0A= + sg_len =3D entry & SG_LIST_LEN_MASK;=0A= +=0A= + sg_addr &=3D SG_LIST_ADDR_MASK;=0A= + addr +=3D SG_LIST_ENTRY_SIZE;=0A= +=0A= + if (sg_len > len - copied) {=0A= + sg_len =3D len - copied;=0A= + }=0A= + if (address_space_rw(&s->dram_as, sg_addr, MEMTXATTRS_UNSPECIFIED,= =0A= + buf + copied, sg_len, to_dram)) {=0A= + return false;=0A= + }=0A= + copied +=3D sg_len;=0A= +=0A= + if (entry & SG_LIST_LEN_LAST) {=0A= + break;=0A= + }=0A= + }=0A= +=0A= + return copied =3D=3D len;=0A= +}=0A= +=0A= +/*=0A= + * Perform an AES/DES/3DES ECB/CBC operation. The source and destination a= re=0A= + * either single contiguous buffers (direct access mode) or scatter-gather= =0A= + * lists (HACE10[18]/[19]), addressed by HACE00/HACE04; the IV/key come fr= om=0A= + * the context buffer (HACE08). For CBC the resulting chaining IV is writt= en=0A= + * back to the context buffer so the driver can continue the chain.=0A= */=0A= static void do_crypt_operation(AspeedHACEState *s, uint32_t cmd)=0A= {=0A= + bool sg_mode =3D cmd & CRYPT_CMD_SRC_SG_CTRL;=0A= uint32_t len =3D s->regs[R_CRYPT_DATA_LEN];=0A= bool encrypt =3D cmd & CRYPT_CMD_ENCRYPT;=0A= g_autoptr(QCryptoCipher) cipher =3D NULL;=0A= @@ -633,6 +678,7 @@ static void do_crypt_operation(AspeedHACEState *s, uint= 32_t cmd)=0A= size_t iv_offset;=0A= size_t blocklen;=0A= size_t keylen;=0A= + bool status;=0A= =0A= if (len =3D=3D 0) {=0A= return;=0A= @@ -686,8 +732,14 @@ static void do_crypt_operation(AspeedHACEState *s, uin= t32_t cmd)=0A= src_buf =3D g_malloc0(len);=0A= dst_buf =3D g_malloc0(len);=0A= =0A= + /* Gather the source into the bounce buffer, per the selected mode. */= =0A= src_addr =3D s->regs[R_CRYPT_SRC];=0A= - if (!crypt_prepare_direct(s, src_addr, src_buf, len, false)) {=0A= + if (sg_mode) {=0A= + status =3D crypt_prepare_sg(s, src_addr, src_buf, len, false);=0A= + } else {=0A= + status =3D crypt_prepare_direct(s, src_addr, src_buf, len, false);= =0A= + }=0A= + if (!status) {=0A= qemu_log_mask(LOG_GUEST_ERROR,=0A= "%s: Failed to read src, addr=3D0x%" HWADDR_PRIx "\n= ",=0A= __func__, src_addr);=0A= @@ -716,8 +768,14 @@ static void do_crypt_operation(AspeedHACEState *s, uin= t32_t cmd)=0A= }=0A= }=0A= =0A= + /* Scatter the result back out, per the selected mode. */=0A= dst_addr =3D s->regs[R_CRYPT_DEST];=0A= - if (!crypt_prepare_direct(s, dst_addr, dst_buf, len, true)) {=0A= + if (sg_mode) {=0A= + status =3D crypt_prepare_sg(s, dst_addr, dst_buf, len, true);=0A= + } else {=0A= + status =3D crypt_prepare_direct(s, dst_addr, dst_buf, len, true);= =0A= + }=0A= + if (!status) {=0A= qemu_log_mask(LOG_GUEST_ERROR,=0A= "%s: Failed to write dst, addr=3D0x%" HWADDR_PRIx "\= n",=0A= __func__, dst_addr);=0A= -- =0A= 2.43.0=0A=