From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f73.google.com (mail-wm1-f73.google.com [209.85.128.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E540B44D03B for ; Wed, 15 Jul 2026 11:59:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.73 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784116763; cv=none; b=lAFXm4/Enhfd1ta7L475i2+nKmkvQ0R5anRl4r4ISZN3lsL7frrD91GlZKs6t+n07nAKBN8W8WR/mrvwRYkCAksVjVrmdCzeXKmhlbKiPGOQdsbg8cHlYk0q4NiIiEvo8L+iCrEpN3+Y5CDoarnaaXn3uSItqamyNLsUl8Zjy98= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784116763; c=relaxed/simple; bh=STqKZu1+JRPT/I5ZbjlCOBueLZbvaon11+KOo0bmUWc=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=YGrJUOFPr7JP6v9/LknIxk9BwnIvOIbqMh1+h/QhzIej+LhcnAi2qYqoP6EV/26ulbbogExK4m7SO+PKdRp2x4Qr7/hbDgzFfB3V/myJRuZ9az0JPdIRmCQ1wFRBFfPpUehSzRO5C5BNDY3J0/1tvEVlqlxjHx6guR9x6F9fiLU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--smostafa.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=CjOVNLpV; arc=none smtp.client-ip=209.85.128.73 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--smostafa.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="CjOVNLpV" Received: by mail-wm1-f73.google.com with SMTP id 5b1f17b1804b1-493b21b1fe8so18018485e9.0 for ; Wed, 15 Jul 2026 04:59:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20251104; t=1784116759; x=1784721559; darn=lists.linux.dev; h=content-type:cc:to:from:subject:message-id:references:mime-version :in-reply-to:date:from:to:cc:subject:date:message-id:reply-to :content-type; bh=2KYF2oL0lGPGcMYNCJmZKWaj3D1T4zoKMpkf+eN5NFY=; b=CjOVNLpVcL6kqj7v6LrNsZLvDT5DDVc1vAX/8fZhGIPdp7T8a/QSaPrbPICS8gjwkd nBJOicsUY5vF5vmGLc0R+CeyqkEp3y135ub8DaKGo9KSvgGyXzgI2PIA8swIvBIfPaOD Up5pJuS9YES5i02ZBweDrzrJ6wJKP5wyVG7FI9i/JS5EYSIRKO9zdfg6Rq5IfgXbngut PHuWk7o49CQqsFp/r8QbzIwrbLbc0rQiuZhavh7gXej0u60/0v0A3srYFhfdisEeD3mv 1hpS7nDtEaycwBOw3YEwX3+YN7j5t8r79F7gMXTdPBFiCEFv8unz4CkCsFOFhsp4zo5l 9u5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784116759; x=1784721559; h=content-type:cc:to:from:subject:message-id:references:mime-version :in-reply-to:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to:content-type; bh=2KYF2oL0lGPGcMYNCJmZKWaj3D1T4zoKMpkf+eN5NFY=; b=B4evwfSThBORkGXY48X60hGrOMEIn5fHAfgPMBrBiUvcf4KGRd/L+HQpnSfzJ7U4s9 zAKuQviNuuFRotUHmNVg17VsXFfGK66nskCMi/0WquHZCke5npa5P6l56clY0tlPEIl1 oRPTRv5Mgi+YfA1QsdA/sc7YAQ35n44PJkFDp2CwN1JCaK2g3TcZNdfcXLtY4P1yrWyJ 9i4VKAp6vdg2Xdy00VF1uuf/mm1Ndll4Nc+t9ZbBIM2JwZVWb6gEHd2tPWFveHPtDSz+ pciV4YQWPTngeAMqvnzd+vuq1hf7stqLq7egqQYgiusXZOixLBzTkTgp0BInaI1F0uG4 BsXg== X-Forwarded-Encrypted: i=1; AHgh+RqMNFZe96sWCM6IaWenyC8EOqHwj47AFkNLqY000kvPgblUkWnzWT1gNl7/aU3D/uzNakXT7/4=@lists.linux.dev X-Gm-Message-State: AOJu0Yw8aPILi0zSN4REbS6xxq4o3wtU5eI4AfMQbj+/BJB4N0jlRk3U PS9+0CspohoShbCj8h/D4HLkXyBQoSoMOr403C8HrBtXjghO/6imgx8vgV02MYkdHtP0cOO0NEc pzzn78hnIq+a6sg== X-Received: from wmap7.prod.google.com ([2002:a7b:cc87:0:b0:487:3739:c5c4]) (user=smostafa job=prod-delivery.src-stubby-dispatcher) by 2002:a05:600c:3f06:b0:495:3c8c:c16a with SMTP id 5b1f17b1804b1-4953c8cc25bmr27539775e9.0.1784116759041; Wed, 15 Jul 2026 04:59:19 -0700 (PDT) Date: Wed, 15 Jul 2026 11:58:46 +0000 In-Reply-To: <20260715115906.2664882-1-smostafa@google.com> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260715115906.2664882-1-smostafa@google.com> X-Mailer: git-send-email 2.55.0.141.g00534a21ce-goog Message-ID: <20260715115906.2664882-6-smostafa@google.com> Subject: [PATCH v7 05/24] iommu/arm-smmu-v3: Move IDR parsing to common functions From: Mostafa Saleh To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, iommu@lists.linux.dev Cc: catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, joro@8bytes.org, jgg@ziepe.ca, mark.rutland@arm.com, qperret@google.com, tabba@google.com, vdonnefort@google.com, sebastianene@google.com, keirf@google.com, Mostafa Saleh Content-Type: text/plain; charset="UTF-8" Move parsing of IDRs to functions so that it can be re-used from the hypervisor. Signed-off-by: Mostafa Saleh --- drivers/iommu/arm/arm-smmu-v3/Makefile | 2 +- .../arm/arm-smmu-v3/arm-smmu-v3-common-lib.c | 184 ++++++++++++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 162 ++------------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 13 ++ 4 files changed, 215 insertions(+), 146 deletions(-) create mode 100644 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-common-lib.c diff --git a/drivers/iommu/arm/arm-smmu-v3/Makefile b/drivers/iommu/arm/arm-smmu-v3/Makefile index 493a659cc66b..c9ce392e6d31 100644 --- a/drivers/iommu/arm/arm-smmu-v3/Makefile +++ b/drivers/iommu/arm/arm-smmu-v3/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_ARM_SMMU_V3) += arm_smmu_v3.o -arm_smmu_v3-y := arm-smmu-v3.o +arm_smmu_v3-y := arm-smmu-v3.o arm-smmu-v3-common-lib.o arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_IOMMUFD) += arm-smmu-v3-iommufd.o arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_SVA) += arm-smmu-v3-sva.o arm_smmu_v3-$(CONFIG_TEGRA241_CMDQV) += tegra241-cmdqv.o diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-common-lib.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-common-lib.c new file mode 100644 index 000000000000..ce0ad88b81e3 --- /dev/null +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-common-lib.c @@ -0,0 +1,184 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2015 ARM Limited + * + * Author: Will Deacon + * Arm SMMUv3 driver functions shared with hypervisor. + */ + +#include "arm-smmu-v3.h" +#include + +#include + +u32 smmu_idr0_features(u32 reg) +{ + u32 features = 0; + + /* 2-level structures */ + if (FIELD_GET(IDR0_ST_LVL, reg) == IDR0_ST_LVL_2LVL) + features |= ARM_SMMU_FEAT_2_LVL_STRTAB; + + if (reg & IDR0_CD2L) + features |= ARM_SMMU_FEAT_2_LVL_CDTAB; + + /* + * Translation table endianness. + * We currently require the same endianness as the CPU, but this + * could be changed later by adding a new IO_PGTABLE_QUIRK. + */ + switch (FIELD_GET(IDR0_TTENDIAN, reg)) { + case IDR0_TTENDIAN_MIXED: + features |= ARM_SMMU_FEAT_TT_LE | ARM_SMMU_FEAT_TT_BE; + break; +#ifdef __BIG_ENDIAN + case IDR0_TTENDIAN_BE: + features |= ARM_SMMU_FEAT_TT_BE; + break; +#else + case IDR0_TTENDIAN_LE: + features |= ARM_SMMU_FEAT_TT_LE; + break; +#endif + } + + /* Boolean feature flags */ + if (IS_ENABLED(CONFIG_PCI_PRI) && reg & IDR0_PRI) + features |= ARM_SMMU_FEAT_PRI; + + if (IS_ENABLED(CONFIG_PCI_ATS) && reg & IDR0_ATS) + features |= ARM_SMMU_FEAT_ATS; + + if (reg & IDR0_SEV) + features |= ARM_SMMU_FEAT_SEV; + + if (reg & IDR0_MSI) + features |= ARM_SMMU_FEAT_MSI; + + if (reg & IDR0_HYP) + features |= ARM_SMMU_FEAT_HYP; + + switch (FIELD_GET(IDR0_STALL_MODEL, reg)) { + case IDR0_STALL_MODEL_FORCE: + features |= ARM_SMMU_FEAT_STALL_FORCE; + fallthrough; + case IDR0_STALL_MODEL_STALL: + features |= ARM_SMMU_FEAT_STALLS; + } + + if (reg & IDR0_S1P) + features |= ARM_SMMU_FEAT_TRANS_S1; + + if (reg & IDR0_S2P) + features |= ARM_SMMU_FEAT_TRANS_S2; + + if ((features & ARM_SMMU_FEAT_TRANS_S1) && + (features & ARM_SMMU_FEAT_TRANS_S2)) + features |= ARM_SMMU_FEAT_NESTING; + + return features; +} + +u32 smmu_idr3_features(u32 reg) +{ + u32 features = 0; + + if (FIELD_GET(IDR3_RIL, reg)) + features |= ARM_SMMU_FEAT_RANGE_INV; + if (FIELD_GET(IDR3_FWB, reg)) + features |= ARM_SMMU_FEAT_S2FWB; + if (FIELD_GET(IDR3_BBM, reg) == 2) + features |= ARM_SMMU_FEAT_BBML2; + return features; +} + +u32 smmu_idr5_to_oas(u32 reg) +{ + switch (FIELD_GET(IDR5_OAS, reg)) { + case IDR5_OAS_32_BIT: + return 32; + case IDR5_OAS_36_BIT: + return 36; + case IDR5_OAS_40_BIT: + return 40; + case IDR5_OAS_42_BIT: + return 42; + case IDR5_OAS_44_BIT: + return 44; + case IDR5_OAS_48_BIT: + return 48; + case IDR5_OAS_52_BIT: + return 52; + } + return 0; +} + +unsigned long smmu_idr5_to_pgsize(u32 reg) +{ + unsigned long pgsize_bitmap = 0; + + if (reg & IDR5_GRAN64K) + pgsize_bitmap |= SZ_64K | SZ_512M; + if (reg & IDR5_GRAN16K) + pgsize_bitmap |= SZ_16K | SZ_32M; + if (reg & IDR5_GRAN4K) + pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G; + return pgsize_bitmap; +} + +unsigned long smmu_iidr_features(u32 reg, unsigned long features) +{ + unsigned int implementer, productid, variant, revision; + + implementer = FIELD_GET(IIDR_IMPLEMENTER, reg); + productid = FIELD_GET(IIDR_PRODUCTID, reg); + variant = FIELD_GET(IIDR_VARIANT, reg); + revision = FIELD_GET(IIDR_REVISION, reg); + + switch (implementer) { + case IIDR_IMPLEMENTER_ARM: + switch (productid) { + case IIDR_PRODUCTID_ARM_MMU_600: + /* Arm erratum 1076982 */ + if (variant == 0 && revision <= 2) + features &= ~ARM_SMMU_FEAT_SEV; + /* Arm erratum 1209401 */ + if (variant < 2) + features &= ~ARM_SMMU_FEAT_NESTING; + break; + case IIDR_PRODUCTID_ARM_MMU_700: + /* Many errata... */ + features &= ~ARM_SMMU_FEAT_BTM; + if (variant < 1 || revision < 1) { + /* Arm errata 2268618, 2812531 */ + features &= ~ARM_SMMU_FEAT_NESTING; + } + break; + case IIDR_PRODUCTID_ARM_MMU_L1: + case IIDR_PRODUCTID_ARM_MMU_S3: + /* Arm errata 3878312/3995052 */ + features &= ~ARM_SMMU_FEAT_BTM; + break; + } + break; + } + return features; +} + +unsigned long smmu_iidr_options(u32 reg, unsigned long options) +{ + unsigned int implementer, productid, variant, revision; + + implementer = FIELD_GET(IIDR_IMPLEMENTER, reg); + productid = FIELD_GET(IIDR_PRODUCTID, reg); + variant = FIELD_GET(IIDR_VARIANT, reg); + revision = FIELD_GET(IIDR_REVISION, reg); + + if ((implementer == IIDR_IMPLEMENTER_ARM) && + (productid == IIDR_PRODUCTID_ARM_MMU_700) && + (variant < 1 || revision < 1)) { + /* Arm erratum 2812531 */ + options |= ARM_SMMU_OPT_CMDQ_FORCE_SYNC; + } + return options; +} diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index cd17a3255312..674ff98706f6 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4759,52 +4759,13 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) return 0; } -#define IIDR_IMPLEMENTER_ARM 0x43b -#define IIDR_PRODUCTID_ARM_MMU_600 0x483 -#define IIDR_PRODUCTID_ARM_MMU_700 0x487 -#define IIDR_PRODUCTID_ARM_MMU_L1 0x48a -#define IIDR_PRODUCTID_ARM_MMU_S3 0x498 - static void arm_smmu_device_iidr_probe(struct arm_smmu_device *smmu) { u32 reg; - unsigned int implementer, productid, variant, revision; reg = readl_relaxed(smmu->base + ARM_SMMU_IIDR); - implementer = FIELD_GET(IIDR_IMPLEMENTER, reg); - productid = FIELD_GET(IIDR_PRODUCTID, reg); - variant = FIELD_GET(IIDR_VARIANT, reg); - revision = FIELD_GET(IIDR_REVISION, reg); - - switch (implementer) { - case IIDR_IMPLEMENTER_ARM: - switch (productid) { - case IIDR_PRODUCTID_ARM_MMU_600: - /* Arm erratum 1076982 */ - if (variant == 0 && revision <= 2) - smmu->features &= ~ARM_SMMU_FEAT_SEV; - /* Arm erratum 1209401 */ - if (variant < 2) - smmu->features &= ~ARM_SMMU_FEAT_NESTING; - break; - case IIDR_PRODUCTID_ARM_MMU_700: - /* Many errata... */ - smmu->features &= ~ARM_SMMU_FEAT_BTM; - if (variant < 1 || revision < 1) { - /* Arm erratum 2812531 */ - smmu->options |= ARM_SMMU_OPT_CMDQ_FORCE_SYNC; - /* Arm errata 2268618, 2812531 */ - smmu->features &= ~ARM_SMMU_FEAT_NESTING; - } - break; - case IIDR_PRODUCTID_ARM_MMU_L1: - case IIDR_PRODUCTID_ARM_MMU_S3: - /* Arm errata 3878312/3995052 */ - smmu->features &= ~ARM_SMMU_FEAT_BTM; - break; - } - break; - } + smmu->features = smmu_iidr_features(reg, smmu->features); + smmu->options = smmu_iidr_options(reg, smmu->options); } static void arm_smmu_get_httu(struct arm_smmu_device *smmu, u32 reg) @@ -4837,57 +4798,17 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) /* IDR0 */ reg = readl_relaxed(smmu->base + ARM_SMMU_IDR0); - /* 2-level structures */ - if (FIELD_GET(IDR0_ST_LVL, reg) == IDR0_ST_LVL_2LVL) - smmu->features |= ARM_SMMU_FEAT_2_LVL_STRTAB; - - if (reg & IDR0_CD2L) - smmu->features |= ARM_SMMU_FEAT_2_LVL_CDTAB; - - /* - * Translation table endianness. - * We currently require the same endianness as the CPU, but this - * could be changed later by adding a new IO_PGTABLE_QUIRK. - */ - switch (FIELD_GET(IDR0_TTENDIAN, reg)) { - case IDR0_TTENDIAN_MIXED: - smmu->features |= ARM_SMMU_FEAT_TT_LE | ARM_SMMU_FEAT_TT_BE; - break; -#ifdef __BIG_ENDIAN - case IDR0_TTENDIAN_BE: - smmu->features |= ARM_SMMU_FEAT_TT_BE; - break; -#else - case IDR0_TTENDIAN_LE: - smmu->features |= ARM_SMMU_FEAT_TT_LE; - break; -#endif - default: + smmu->features |= smmu_idr0_features(reg); + if (!(smmu->features & (ARM_SMMU_FEAT_TT_LE | ARM_SMMU_FEAT_TT_BE))) { dev_err(smmu->dev, "unknown/unsupported TT endianness!\n"); return -ENXIO; } - - /* Boolean feature flags */ - if (IS_ENABLED(CONFIG_PCI_PRI) && reg & IDR0_PRI) - smmu->features |= ARM_SMMU_FEAT_PRI; - - if (IS_ENABLED(CONFIG_PCI_ATS) && reg & IDR0_ATS) - smmu->features |= ARM_SMMU_FEAT_ATS; - - if (reg & IDR0_SEV) - smmu->features |= ARM_SMMU_FEAT_SEV; - - if (reg & IDR0_MSI) { - smmu->features |= ARM_SMMU_FEAT_MSI; - if (coherent && !disable_msipolling) - smmu->options |= ARM_SMMU_OPT_MSIPOLL; - } - - if (reg & IDR0_HYP) { - smmu->features |= ARM_SMMU_FEAT_HYP; - if (cpus_have_cap(ARM64_HAS_VIRT_HOST_EXTN)) - smmu->features |= ARM_SMMU_FEAT_E2H; - } + if (coherent && !disable_msipolling && + smmu->features & ARM_SMMU_FEAT_MSI) + smmu->options |= ARM_SMMU_OPT_MSIPOLL; + if (smmu->features & ARM_SMMU_FEAT_HYP && + cpus_have_cap(ARM64_HAS_VIRT_HOST_EXTN)) + smmu->features |= ARM_SMMU_FEAT_E2H; arm_smmu_get_httu(smmu, reg); @@ -4899,21 +4820,7 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) dev_warn(smmu->dev, "IDR0.COHACC overridden by FW configuration (%s)\n", str_true_false(coherent)); - switch (FIELD_GET(IDR0_STALL_MODEL, reg)) { - case IDR0_STALL_MODEL_FORCE: - smmu->features |= ARM_SMMU_FEAT_STALL_FORCE; - fallthrough; - case IDR0_STALL_MODEL_STALL: - smmu->features |= ARM_SMMU_FEAT_STALLS; - } - - if (reg & IDR0_S1P) - smmu->features |= ARM_SMMU_FEAT_TRANS_S1; - - if (reg & IDR0_S2P) - smmu->features |= ARM_SMMU_FEAT_TRANS_S2; - - if (!(reg & (IDR0_S1P | IDR0_S2P))) { + if (!(smmu->features & (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2))) { dev_err(smmu->dev, "no translation support!\n"); return -ENXIO; } @@ -4972,13 +4879,7 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) /* IDR3 */ reg = readl_relaxed(smmu->base + ARM_SMMU_IDR3); - if (FIELD_GET(IDR3_RIL, reg)) - smmu->features |= ARM_SMMU_FEAT_RANGE_INV; - if (FIELD_GET(IDR3_FWB, reg)) - smmu->features |= ARM_SMMU_FEAT_S2FWB; - - if (FIELD_GET(IDR3_BBM, reg) == 2) - smmu->features |= ARM_SMMU_FEAT_BBML2; + smmu->features |= smmu_idr3_features(reg); /* IDR5 */ reg = readl_relaxed(smmu->base + ARM_SMMU_IDR5); @@ -4987,43 +4888,18 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) smmu->evtq.max_stalls = FIELD_GET(IDR5_STALL_MAX, reg); /* Page sizes */ - if (reg & IDR5_GRAN64K) - smmu->pgsize_bitmap |= SZ_64K | SZ_512M; - if (reg & IDR5_GRAN16K) - smmu->pgsize_bitmap |= SZ_16K | SZ_32M; - if (reg & IDR5_GRAN4K) - smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G; + smmu->pgsize_bitmap = smmu_idr5_to_pgsize(reg); /* Input address size */ if (FIELD_GET(IDR5_VAX, reg) == IDR5_VAX_52_BIT) smmu->features |= ARM_SMMU_FEAT_VAX; - /* Output address size */ - switch (FIELD_GET(IDR5_OAS, reg)) { - case IDR5_OAS_32_BIT: - smmu->oas = 32; - break; - case IDR5_OAS_36_BIT: - smmu->oas = 36; - break; - case IDR5_OAS_40_BIT: - smmu->oas = 40; - break; - case IDR5_OAS_42_BIT: - smmu->oas = 42; - break; - case IDR5_OAS_44_BIT: - smmu->oas = 44; - break; - case IDR5_OAS_52_BIT: - smmu->oas = 52; + smmu->oas = smmu_idr5_to_oas(reg); + if (smmu->oas == 52) smmu->pgsize_bitmap |= 1ULL << 42; /* 4TB */ - break; - default: + else if (!smmu->oas) { dev_info(smmu->dev, - "unknown output address size. Truncating to 48-bit\n"); - fallthrough; - case IDR5_OAS_48_BIT: + "unknown output address size. Truncating to 48-bit\n"); smmu->oas = 48; } @@ -5032,10 +4908,6 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) dev_warn(smmu->dev, "failed to set DMA mask for table walker\n"); - if ((smmu->features & ARM_SMMU_FEAT_TRANS_S1) && - (smmu->features & ARM_SMMU_FEAT_TRANS_S2)) - smmu->features |= ARM_SMMU_FEAT_NESTING; - arm_smmu_device_iidr_probe(smmu); if (arm_smmu_sva_supported(smmu)) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 494e55a2dc34..842d0c9b883c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -84,6 +84,12 @@ struct arm_vsmmu; #define IIDR_REVISION GENMASK(15, 12) #define IIDR_IMPLEMENTER GENMASK(11, 0) +#define IIDR_IMPLEMENTER_ARM 0x43b +#define IIDR_PRODUCTID_ARM_MMU_600 0x483 +#define IIDR_PRODUCTID_ARM_MMU_700 0x487 +#define IIDR_PRODUCTID_ARM_MMU_L1 0x48a +#define IIDR_PRODUCTID_ARM_MMU_S3 0x498 + #define ARM_SMMU_AIDR 0x1C #define ARM_SMMU_CR0 0x20 @@ -1212,6 +1218,13 @@ int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, struct arm_smmu_cmd *cmds, int n, bool sync); +u32 smmu_idr0_features(u32 reg); +u32 smmu_idr3_features(u32 reg); +u32 smmu_idr5_to_oas(u32 reg); +unsigned long smmu_idr5_to_pgsize(u32 reg); +unsigned long smmu_iidr_features(u32 reg, unsigned long features); +unsigned long smmu_iidr_options(u32 reg, unsigned long options); + /* Queue functions shared between kernel and hyp. */ static inline bool queue_has_space(struct arm_smmu_ll_queue *q, u32 n) { -- 2.55.0.141.g00534a21ce-goog