From: sashiko-bot@kernel.org
To: "Peng Fan (OSS)" <peng.fan@oss.nxp.com>
Cc: conor+dt@kernel.org, imx@lists.linux.dev, robh@kernel.org,
Frank.Li@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH 2/9] arm64: dts: imx8ulp: Add I3C2 controller node
Date: Wed, 15 Jul 2026 12:42:07 +0000 [thread overview]
Message-ID: <20260715124208.2B48C1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260715-imx8ulp-dts-v1-2-19651358b599@nxp.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The device tree assigns a dummy clock for 'slow_clk', contradicting the commit message which states it is configured to use the 24 MHz PCC3-gated clock.
--
--- Patch [2]: [PATCH 2/9] arm64: dts: imx8ulp: Add I3C2 controller node ---
commit 56028cef3837517bbf3f1ac9d58c6983788955ee
Author: Peng Fan <peng.fan@nxp.com>
arm64: dts: imx8ulp: Add I3C2 controller node
This commit adds the I3C2 node to the imx8ulp device tree using the
Silvaco I3C master IP. It also configures the controller's interrupts
and clock sources.
> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> index 5438958176985..c82c3388cbe79 100644
> --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
[ ... ]
> @@ -361,6 +361,22 @@ tpm5: tpm@29340000 {
[ ... ]
> + i3c2: i3c@29360000 {
> + compatible = "silvaco,i3c-master-v1";
> + reg = <0x29360000 0x10000>;
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <3>;
> + #size-cells = <0>;
> + clocks = <&pcc3 IMX8ULP_CLK_I3C2>,
> + <&pcc3 IMX8ULP_CLK_I3C2>,
> + <&cgc1 IMX8ULP_CLK_DUMMY>;
> + clock-names = "pclk", "fast_clk", "slow_clk";
[Severity: Medium]
Does this clock assignment match the intention described in the commit message?
The commit message states that the PCC3-gated clock is configured "for pclk,
fast_clk and slow_clk". However, the device tree node assigns the dummy clock
(&cgc1 IMX8ULP_CLK_DUMMY) for slow_clk instead.
Should slow_clk be using &pcc3 IMX8ULP_CLK_I3C2 as described, or should the
commit message be updated to reflect the use of the dummy clock?
> + assigned-clocks = <&pcc3 IMX8ULP_CLK_I3C2>;
> + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
> + assigned-clock-rates = <24000000>;
> + status = "disabled";
> + };
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260715-imx8ulp-dts-v1-0-19651358b599@nxp.com?part=2
next prev parent reply other threads:[~2026-07-15 12:42 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-15 12:33 [PATCH 0/9] arm64: dts: imx8ulp: Device tree updates for i.MX 8ULP EVK boards Peng Fan (OSS)
2026-07-15 12:33 ` [PATCH 1/9] arm64: dts: imx8ulp: Add DMA channel properties and use eDMA flag macros Peng Fan (OSS)
2026-07-15 12:33 ` [PATCH 2/9] arm64: dts: imx8ulp: Add I3C2 controller node Peng Fan (OSS)
2026-07-15 12:42 ` sashiko-bot [this message]
2026-07-15 15:12 ` Frank Li
2026-07-15 12:33 ` [PATCH 3/9] arm64: dts: imx8ulp: Correct SRAM node address and size to cover full SSRAM P2 Peng Fan (OSS)
2026-07-15 12:47 ` sashiko-bot
2026-07-15 15:14 ` Frank Li
2026-07-15 12:33 ` [PATCH 4/9] arm64: dts: imx8ulp: Add assigned clock properties for LPUART nodes Peng Fan (OSS)
2026-07-15 12:33 ` [PATCH 5/9] arm64: dts: imx8ulp-evk: Add gpio-keys node for power button Peng Fan (OSS)
2026-07-15 12:33 ` [PATCH 6/9] arm64: dts: imx8ulp-evk: Enable LPUART6 for Bluetooth Peng Fan (OSS)
2026-07-15 15:17 ` Frank Li
2026-07-15 12:33 ` [PATCH 7/9] arm64: dts: imx8ulp-evk: Enable LPUART7 Peng Fan (OSS)
2026-07-15 15:18 ` Frank Li
2026-07-15 12:33 ` [PATCH 8/9] arm64: dts: imx8ulp-evk: Change the values of some PCRs of ENET Peng Fan (OSS)
2026-07-15 12:33 ` [PATCH 9/9] arm64: dts: imx8ulp-9x9-evk: Rename model string to reflect die size Peng Fan (OSS)
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