From: sashiko-bot@kernel.org
To: "Ravi Hothi" <ravi.hothi@oss.qualcomm.com>
Cc: robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v3 2/2] pinctrl: qcom: milos-lpass-lpi: Add Eliza LPASS LPI TLMM
Date: Wed, 15 Jul 2026 13:30:26 +0000 [thread overview]
Message-ID: <20260715133026.CB9AE1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260715132150.1322663-3-ravi.hothi@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [High] This problem wasn't introduced by this patch, but lpi_config_set() unconditionally overwrites unspecified pin configuration parameters (such as pull bias, drive strength, and output enable) with default values, rather than preserving the existing register state. This breaks the pinconf API contract, especially when changing a single parameter dynamically.
--
--- Patch [2]: [PATCH v3 2/2] pinctrl: qcom: milos-lpass-lpi: Add Eliza LPASS LPI TLMM ---
commit 0b7a3c2b301461d37d7084e97a33317743f82c3e
Author: Ravi Hothi <ravi.hothi@oss.qualcomm.com>
pinctrl: qcom: milos-lpass-lpi: Add Eliza LPASS LPI TLMM
Eliza SoC has the same LPASS LPI pin mux functions as Milos but the
slew rate control is in the same GPIO config register rather than a
separate register. Add a new variant data struct with updated slew
offsets and LPI_FLAG_SLEW_RATE_SAME_REG flag, reusing the existing
pin descriptors and function table from Milos.
> diff --git a/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c
> index 72b8ffd97860b..cb4934cd6f757 100644
> --- a/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c
> +++ b/drivers/pinctrl/qcom/pinctrl-milos-lpass-lpi.c
[ ... ]
> @@ -196,8 +223,21 @@ static const struct lpi_pinctrl_variant_data milos_lpi_data = {
> .nfunctions = ARRAY_SIZE(milos_functions),
> };
>
> +static const struct lpi_pinctrl_variant_data eliza_lpi_data = {
> + .pins = milos_lpi_pins,
> + .npins = ARRAY_SIZE(milos_lpi_pins),
> + .groups = eliza_groups,
> + .ngroups = ARRAY_SIZE(eliza_groups),
> + .functions = milos_functions,
> + .nfunctions = ARRAY_SIZE(milos_functions),
> + .flags = LPI_FLAG_SLEW_RATE_SAME_REG,
> +};
[Severity: High]
This isn't a bug introduced by this patch, but since Eliza will use the shared
LPASS LPI infrastructure, does the core lpi_config_set() function overwrite
unspecified pin configuration parameters?
Looking at drivers/pinctrl/qcom/pinctrl-lpass-lpi.c:lpi_config_set(), variables
are initialized to defaults instead of the current hardware state:
unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2;
bool value, output_enabled = false;
After parsing explicitly provided configs, these defaults are unconditionally
written back to the register:
lpi_gpio_read_reg(pctrl, group, LPI_GPIO_CFG_REG, &val);
u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK);
u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength),
LPI_GPIO_OUT_STRENGTH_MASK);
u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK);
lpi_gpio_write_reg(pctrl, group, LPI_GPIO_CFG_REG, val);
Will this cause a partial pinconf update (or a dynamic change to a single GPIO
property) to wipe out the pin's existing drive strength and pull-up/down bias,
potentially breaking audio interface signaling constraints?
> static const struct of_device_id lpi_pinctrl_of_match[] = {
> {
> + .compatible = "qcom,eliza-lpass-lpi-pinctrl",
> + .data = &eliza_lpi_data,
> + }, {
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260715132150.1322663-1-ravi.hothi@oss.qualcomm.com?part=2
prev parent reply other threads:[~2026-07-15 13:30 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-15 13:21 [PATCH v3 0/2] pinctrl: qcom: Add Eliza LPASS LPI support Ravi Hothi
2026-07-15 13:21 ` [PATCH v3 1/2] dt-bindings: pinctrl: qcom,milos-lpass-lpi-pinctrl: Add Eliza pinctrl Ravi Hothi
2026-07-15 13:35 ` sashiko-bot
2026-07-15 13:21 ` [PATCH v3 2/2] pinctrl: qcom: milos-lpass-lpi: Add Eliza LPASS LPI TLMM Ravi Hothi
2026-07-15 13:30 ` sashiko-bot [this message]
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