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Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB9457 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Tomasz Siemek [why] CONFIG_DRM_AMD_DC_DCN4_2 were readded to DAL by mistake resulting in parts of dcn42 3dlut code not being compiled. [how] Remove readded CONFIG_DRM_AMD_DC_DCN4_2 guards. Reviewed-by: Rafal Ostrowski Signed-off-by: Tomasz Siemek Signed-off-by: Wayne Lin --- drivers/gpu/drm/amd/display/dc/dc.h | 4 ---- drivers/gpu/drm/amd/display/dc/dc_types.h | 8 -------- drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 2 -- drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c | 7 +------ 4 files changed, 1 insertion(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e1b7d359d917..436277acd034 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1508,13 +1508,9 @@ union dc_plane_cm_flags { unsigned int blend_enable : 1; /* whether legacy (lut3d_func) or DMA is valid */ unsigned int lut3d_dma_enable : 1; -#if defined(CONFIG_DRM_AMD_DC_DCN4_2) /* RMCM lut to be used instead of MCM */ unsigned int rmcm_enable : 1; unsigned int reserved: 27; -#else - unsigned int reserved: 28; -#endif } bits; }; diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 5ba7a2fffcf0..fccf9cb359f0 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -1414,28 +1414,20 @@ enum dc_cm_lut_swizzle { enum dc_cm_lut_pixel_format { CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12MSB, -#if defined(CONFIG_DRM_AMD_DC_DCN4_2) CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12MSB, -#endif CM_LUT_PIXEL_FORMAT_RGBA16161616_UNORM_12LSB, -#if defined(CONFIG_DRM_AMD_DC_DCN4_2) CM_LUT_PIXEL_FORMAT_BGRA16161616_UNORM_12LSB, -#endif CM_LUT_PIXEL_FORMAT_RGBA16161616_FLOAT_FP1_5_10, -#if defined(CONFIG_DRM_AMD_DC_DCN4_2) CM_LUT_PIXEL_FORMAT_BGRA16161616_FLOAT_FP1_5_10 -#endif }; enum dc_cm_lut_size { CM_LUT_SIZE_NONE, CM_LUT_SIZE_999, CM_LUT_SIZE_171717, -#if defined(CONFIG_DRM_AMD_DC_DCN4_2) CM_LUT_SIZE_333333, CM_LUT_SIZE_454545, CM_LUT_SIZE_656565, -#endif }; #ifndef TRIM_CM2 diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 1862670ea042..308085d24775 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -515,12 +515,10 @@ void dcn401_populate_mcm_luts(struct dc *dc, /* Select width based on the requested LUT size */ switch (cm->lut3d_dma.size) { -#if defined(CONFIG_DRM_AMD_DC_DCN4_2) case CM_LUT_SIZE_333333: if (dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_33) width = hubp_3dlut_fl_width_33; break; -#endif // CONFIG_DRM_AMD_DC_DCN4_2 case CM_LUT_SIZE_171717: width = hubp_3dlut_fl_width_17; break; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c index cc8e96ffe7d1..4376bf26f4ce 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c @@ -470,7 +470,6 @@ static bool dc_is_rmcm_3dlut_supported(struct hubp *hubp, struct mpc *mpc) return false; } -#if defined(CONFIG_DRM_AMD_DC_DCN4_2) static bool is_rmcm_3dlut_fl_supported(struct dc *dc) { /* size was previously hard-coded to TRANSFORMED in local_mcm, @@ -480,7 +479,6 @@ static bool is_rmcm_3dlut_fl_supported(struct dc *dc) return false; return dc->caps.color.mpc.rmcm_3d_lut_caps.lut_dim_caps.dim_17 != 0u; } -#endif static void dcn42_set_mcm_location_post_blend(struct dc *dc, struct pipe_ctx *pipe_ctx, bool bPostBlend) { @@ -724,9 +722,8 @@ void dcn42_populate_mcm_luts(struct dc *dc, false); //RMCM - 3dLUT+Shaper -#if defined(CONFIG_DRM_AMD_DC_DCN4_2) if (cm->flags.bits.rmcm_enable && - is_rmcm_3dlut_fl_supported(dc)) { + is_rmcm_3dlut_fl_supported(dc)) dcn42_program_rmcm_luts( hubp, pipe_ctx, @@ -734,8 +731,6 @@ void dcn42_populate_mcm_luts(struct dc *dc, mpc, lut_bank_a, mpcc_id); - } -#endif /* CONFIG_DRM_AMD_DC_DCN4_2 */ /* 1D LUT */ { -- 2.43.0