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Wed, 15 Jul 2026 08:45:31 -0500 From: Wayne Lin To: CC: Harry Wentland , Leo Li , Aurabindo Pillai , Roman Li , Wayne Lin , Tom Chung , "Fangzhi Zuo" , Dan Wheeler , Ray Wu , Ivan Lipski , Alex Hung , James Lin , Chenyu Chen , Tomasz Siemek , Alvin Lee Subject: [PATCH 11/70] drm/amd/display: Refactor DPP_PROGRAM_GAMUT_REMAP to drop pipe_ctx param Date: Wed, 15 Jul 2026 21:37:21 +0800 Message-ID: <20260715134432.1975118-12-Wayne.Lin@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715134432.1975118-1-Wayne.Lin@amd.com> References: <20260715134432.1975118-1-Wayne.Lin@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F4:EE_|CH1PR12MB9693:EE_ X-MS-Office365-Filtering-Correlation-Id: c253ca27-7fab-440d-57d7-08dee27762de X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|1800799024|23010399003|36860700016|376014|11063799006|6133799003|56012099006|10067099003|3023799007|22082099003|18002099003; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: NrAHWxtapguJ0K0/wC7U0f2yll5supLO3lEfiV1jbrYrdu89zhj0o4tG25Yz/SCmB40iZPsaXzb7dtIIN9ifdlXDaG4trUbl+IzhzYxftZixp3jnjuiTbbodH2Aq6xf5JS5VYhxTGyGMCRx7dd3sO73ymiz5vBmr7P3EI2ViyQj/19XkfPlHdwMPW4DwNr4gzlN/8m/hTwEMw/I2sj6pW1F+bXJp1oazjPh8ZOE7DVwEdbZqFdjhMIQoikj+3T9cDBC4OBh0t3KOmZOmgtkR8G2HlRGG6oIvhNh7JyRHQOdzGs/3F9LYRqy+dp1iTEYOWHiiZSSAysTzit23iHQiOXpz3lhQ85MElrM4grNVSXWvJo+WoESIL24zS5BcaCSnauqBbHRaRdGt/78qza2MwFgIygY2PpwouMe+HXKh8M1F+b64hEaxKmMlDg4Il0lP X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2026 13:45:51.9645 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c253ca27-7fab-440d-57d7-08dee27762de X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PR12MB9693 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Tomasz Siemek [why] Pipe_ctx shouldn't be passed as block sequence block parameter. [how] - Adjust program_gamut_remap_params struct. - Adjust program_gamut_remap interface and implementations. - Adjust program_gamut_remap callsites to match new signature. Reviewed-by: Alvin Lee Signed-off-by: Tomasz Siemek Signed-off-by: Wayne Lin --- drivers/gpu/drm/amd/display/dc/core/dc.c | 10 ++++- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 37 +++++++++++++++---- .../amd/display/dc/hwss/dce110/dce110_hwseq.c | 11 ++++-- .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 20 ++++++---- .../amd/display/dc/hwss/dcn10/dcn10_hwseq.h | 2 +- .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 2 +- .../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 24 +++++++----- .../amd/display/dc/hwss/dcn30/dcn30_hwseq.h | 2 +- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 25 +++++++------ .../amd/display/dc/hwss/dcn401/dcn401_hwseq.h | 2 +- .../drm/amd/display/dc/hwss/hw_sequencer.h | 12 ++++-- 11 files changed, 99 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 7b3a83ba7459..188615873791 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -831,7 +831,15 @@ bool dc_stream_set_gamut_remap(struct dc *dc, const struct dc_stream_state *stre for (i = 0; i < MAX_PIPES; i++) { if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) { pipes = &dc->current_state->res_ctx.pipe_ctx[i]; - dc->hwss.program_gamut_remap(pipes); + dc->hwss.program_gamut_remap(&(struct program_gamut_remap_params) { + .xfm = pipes->plane_res.xfm, + .dpp = pipes->plane_res.dpp, + .mpc = dc->res_pool->mpc, + .mpcc_id = pipes->plane_res.mpcc_inst, + .stream = pipes->stream, + .plane = pipes->plane_state, + .is_top_pipe = pipes->top_pipe == NULL, + }); ret = true; } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index e47c8cf5d036..4f30d9ac4a0d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -1069,7 +1069,14 @@ void hwss_build_fast_sequence(struct dc *dc, if (dc->hwss.program_gamut_remap && (current_mpc_pipe->plane_state->update_bits.gamut_remap_change || current_mpc_pipe->stream->update_flags.bits.gamut_remap)) { - block_sequence[*num_steps].params.program_gamut_remap_params.pipe_ctx = current_mpc_pipe; + struct program_gamut_remap_params *params = &block_sequence[*num_steps].params.program_gamut_remap_params; + params->dpp = current_mpc_pipe->plane_res.dpp; + params->mpc = dc->res_pool->mpc; + params->xfm = current_mpc_pipe->plane_res.xfm; + params->mpcc_id = current_mpc_pipe->plane_res.hubp->inst; + params->plane = current_mpc_pipe->plane_state; + params->stream = current_mpc_pipe->stream; + params->is_top_pipe = current_mpc_pipe->top_pipe == NULL; block_sequence[*num_steps].func = DPP_PROGRAM_GAMUT_REMAP; (*num_steps)++; } @@ -1236,7 +1243,8 @@ void hwss_execute_sequence(struct dc *dc, params->set_input_transfer_func_params.plane_state); break; case DPP_PROGRAM_GAMUT_REMAP: - hwss_program_gamut_remap(params); + if (dc->hwss.program_gamut_remap) + dc->hwss.program_gamut_remap(¶ms->program_gamut_remap_params); break; case HUBP_ENABLE_3DLUT_FL: hwss_hubp_enable_3dlut_fl(params); @@ -1779,7 +1787,14 @@ void hwss_add_dpp_program_gamut_remap(struct block_sequence_state *seq_state, struct pipe_ctx *pipe_ctx) { if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { - seq_state->steps[*seq_state->num_steps].params.program_gamut_remap_params.pipe_ctx = pipe_ctx; + struct program_gamut_remap_params *params = &seq_state->steps[*seq_state->num_steps].params.program_gamut_remap_params; + params->xfm = pipe_ctx->plane_res.xfm; + params->dpp = pipe_ctx->plane_res.dpp; + params->mpc = pipe_ctx->stream->ctx->dc->res_pool->mpc; + params->mpcc_id = pipe_ctx->plane_res.hubp->inst; + params->plane = pipe_ctx->plane_state; + params->stream = pipe_ctx->stream; + params->is_top_pipe = pipe_ctx->top_pipe == NULL; seq_state->steps[*seq_state->num_steps].func = DPP_PROGRAM_GAMUT_REMAP; (*seq_state->num_steps)++; } @@ -3617,12 +3632,20 @@ void hwss_set_cursor_sdr_white_level(union block_sequence_params *params) dc->hwss.set_cursor_sdr_white_level(pipe_ctx); } -void hwss_program_gamut_remap(union block_sequence_params *params) +void hwss_program_gamut_remap(struct pipe_ctx *pipe_ctx) { - struct dc *dc = params->program_gamut_remap_params.pipe_ctx->stream->ctx->dc; + struct dc *dc = pipe_ctx->stream->ctx->dc; - if (dc && dc->hwss.program_gamut_remap) - dc->hwss.program_gamut_remap(params->program_gamut_remap_params.pipe_ctx); + if (dc->hwss.program_gamut_remap) + dc->hwss.program_gamut_remap(&(struct program_gamut_remap_params) { + .xfm = pipe_ctx->plane_res.xfm, + .dpp = pipe_ctx->plane_res.dpp, + .mpc = dc->res_pool->mpc, + .mpcc_id = pipe_ctx->plane_res.hubp->inst, + .stream = pipe_ctx->stream, + .plane = pipe_ctx->plane_state, + .is_top_pipe = pipe_ctx->top_pipe == NULL, + }); } void hwss_program_output_csc(union block_sequence_params *params) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index cce4f3065575..74b046ab3bc3 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -2810,23 +2810,26 @@ static void program_surface_visibility(const struct dc *dc, } -static void program_gamut_remap(struct pipe_ctx *pipe_ctx) +static void program_gamut_remap(struct program_gamut_remap_params *params) { + struct transform *xfm = params->xfm; + const struct dc_stream_state *stream = params->stream; int i = 0; struct xfm_grph_csc_adjustment adjust; + memset(&adjust, 0, sizeof(adjust)); adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; - if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { + if (stream->gamut_remap_matrix.enable_remap == true) { adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) adjust.temperature_matrix[i] = - pipe_ctx->stream->gamut_remap_matrix.matrix[i]; + stream->gamut_remap_matrix.matrix[i]; } - pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); + xfm->funcs->transform_set_gamut_remap(xfm, &adjust); } static void update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index f75a1794ae2a..8c636698d6d4 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -2814,28 +2814,32 @@ static void dcn10_enable_plane( } -void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx) +void dcn10_program_gamut_remap(struct program_gamut_remap_params *params) { + struct dpp *dpp = params->dpp; + const struct dc_stream_state *stream = params->stream; + const struct dc_plane_state *plane = params->plane; int i = 0; struct dpp_grph_csc_adjustment adjust; + memset(&adjust, 0, sizeof(adjust)); adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; - if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { + if (stream->gamut_remap_matrix.enable_remap == true) { adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) adjust.temperature_matrix[i] = - pipe_ctx->stream->gamut_remap_matrix.matrix[i]; - } else if (pipe_ctx->plane_state && - pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) { + stream->gamut_remap_matrix.matrix[i]; + } else if (plane && + plane->gamut_remap_matrix.enable_remap == true) { adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) adjust.temperature_matrix[i] = - pipe_ctx->plane_state->gamut_remap_matrix.matrix[i]; + plane->gamut_remap_matrix.matrix[i]; } - pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust); + dpp->funcs->dpp_set_gamut_remap(dpp, &adjust); } @@ -3152,7 +3156,7 @@ static void dcn10_update_dchubp_dpp( if (plane_state->update_bits.full_update) { /*gamut remap*/ - dc->hwss.program_gamut_remap(pipe_ctx); + hwss_program_gamut_remap(pipe_ctx); dc->hwss.program_output_csc(dc, pipe_ctx, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h index 476095c5dd0c..162972dfdbe8 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h @@ -108,7 +108,7 @@ void dcn10_program_pipe( struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_state *context); -void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx); +void dcn10_program_gamut_remap(struct program_gamut_remap_params *params); void dcn10_init_hw(struct dc *dc); void dcn10_init_pipes(struct dc *dc, struct dc_state *context); void dcn10_power_down_on_boot(struct dc *dc); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index 95e5b6a6ba0f..83794d5b838c 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -1815,7 +1815,7 @@ void dcn20_update_dchubp_dpp( || plane_state->update_bits.gamut_remap_change || pipe_ctx->stream->update_flags.bits.out_csc) { /* dpp/cm gamut remap*/ - dc->hwss.program_gamut_remap(pipe_ctx); + hwss_program_gamut_remap(pipe_ctx); /*call the dcn2 method which uses mpc csc*/ dc->hwss.program_output_csc(dc, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c index aa7707b2b25b..82a662efa49f 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c @@ -357,37 +357,41 @@ bool dcn30_set_input_transfer_func(struct dc *dc, return result; } -void dcn30_program_gamut_remap(struct pipe_ctx *pipe_ctx) +void dcn30_program_gamut_remap(struct program_gamut_remap_params *params) { + struct dpp *dpp = params->dpp; + struct mpc *mpc = params->mpc; + int mpcc_id = params->mpcc_id; + const struct dc_stream_state *stream = params->stream; + const struct dc_plane_state *plane = params->plane; + bool is_top_pipe = params->is_top_pipe; int i = 0; struct dpp_grph_csc_adjustment dpp_adjust; struct mpc_grph_gamut_adjustment mpc_adjust; - int mpcc_id = pipe_ctx->plane_res.hubp->inst; - struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; memset(&dpp_adjust, 0, sizeof(dpp_adjust)); dpp_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; - if (pipe_ctx->plane_state && - pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) { + if (plane && + plane->gamut_remap_matrix.enable_remap == true) { dpp_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) dpp_adjust.temperature_matrix[i] = - pipe_ctx->plane_state->gamut_remap_matrix.matrix[i]; + plane->gamut_remap_matrix.matrix[i]; } - pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, + dpp->funcs->dpp_set_gamut_remap(dpp, &dpp_adjust); memset(&mpc_adjust, 0, sizeof(mpc_adjust)); mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; - if (pipe_ctx->top_pipe == NULL) { - if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { + if (is_top_pipe) { + if (stream->gamut_remap_matrix.enable_remap == true) { mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) mpc_adjust.temperature_matrix[i] = - pipe_ctx->stream->gamut_remap_matrix.matrix[i]; + stream->gamut_remap_matrix.matrix[i]; } } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h index a963d360a368..4182cf399424 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h @@ -63,7 +63,7 @@ bool dcn30_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state); -void dcn30_program_gamut_remap(struct pipe_ctx *pipe_ctx); +void dcn30_program_gamut_remap(struct program_gamut_remap_params *params); bool dcn30_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 308085d24775..5c1ba5d88c7a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -89,28 +89,31 @@ void dcn401_initialize_min_clocks(struct dc *dc) true); } -void dcn401_program_gamut_remap(struct pipe_ctx *pipe_ctx) +void dcn401_program_gamut_remap(struct program_gamut_remap_params *params) { + struct mpc *mpc = params->mpc; + int mpcc_id = params->mpcc_id; + const struct dc_stream_state *stream = params->stream; + const struct dc_plane_state *plane = params->plane; + bool is_top_pipe = params->is_top_pipe; unsigned int i = 0; struct mpc_grph_gamut_adjustment mpc_adjust; - unsigned int mpcc_id = pipe_ctx->plane_res.mpcc_inst; - struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; //For now assert if location is not pre-blend - if (pipe_ctx->plane_state) - ASSERT(pipe_ctx->plane_state->mcm_location == MPCC_MOVABLE_CM_LOCATION_BEFORE); + if (plane) + ASSERT(plane->mcm_location == MPCC_MOVABLE_CM_LOCATION_BEFORE); // program MPCC_MCM_FIRST_GAMUT_REMAP memset(&mpc_adjust, 0, sizeof(mpc_adjust)); mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; mpc_adjust.mpcc_gamut_remap_block_id = MPCC_MCM_FIRST_GAMUT_REMAP; - if (pipe_ctx->plane_state && - pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) { + if (plane && + plane->gamut_remap_matrix.enable_remap == true) { mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) mpc_adjust.temperature_matrix[i] = - pipe_ctx->plane_state->gamut_remap_matrix.matrix[i]; + plane->gamut_remap_matrix.matrix[i]; } mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust); @@ -126,12 +129,12 @@ void dcn401_program_gamut_remap(struct pipe_ctx *pipe_ctx) mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; mpc_adjust.mpcc_gamut_remap_block_id = MPCC_OGAM_GAMUT_REMAP; - if (pipe_ctx->top_pipe == NULL) { - if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { + if (is_top_pipe) { + if (stream->gamut_remap_matrix.enable_remap == true) { mpc_adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) mpc_adjust.temperature_matrix[i] = - pipe_ctx->stream->gamut_remap_matrix.matrix[i]; + stream->gamut_remap_matrix.matrix[i]; } } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h index a760050eea8c..6d2e93149811 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h @@ -32,7 +32,7 @@ struct ips_ono_region_state { uint32_t current_pwr_state; }; -void dcn401_program_gamut_remap(struct pipe_ctx *pipe_ctx); +void dcn401_program_gamut_remap(struct program_gamut_remap_params *params); void dcn401_init_hw(struct dc *dc); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index 65df8002d3d7..d8398b39a119 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -95,7 +95,13 @@ struct set_input_transfer_func_params { }; struct program_gamut_remap_params { - struct pipe_ctx *pipe_ctx; + struct transform *xfm; + struct dpp *dpp; + struct mpc *mpc; + int mpcc_id; + const struct dc_stream_state *stream; + const struct dc_plane_state *plane; + bool is_top_pipe; }; struct hubp_enable_3dlut_fl_params { @@ -1389,7 +1395,7 @@ struct hw_sequencer_funcs { void (*program_cursor_offload_now)(struct dc *dc, const struct pipe_ctx *pipe); /* Colour Related */ - void (*program_gamut_remap)(struct pipe_ctx *pipe_ctx); + void (*program_gamut_remap)(struct program_gamut_remap_params *params); void (*program_output_csc)(struct dc *dc, struct pipe_ctx *pipe_ctx, enum dc_color_space colorspace, uint16_t *matrix, int opp_id); @@ -1940,7 +1946,7 @@ void hwss_set_cursor_position(union block_sequence_params *params); void hwss_set_cursor_sdr_white_level(union block_sequence_params *params); -void hwss_program_gamut_remap(union block_sequence_params *params); +void hwss_program_gamut_remap(struct pipe_ctx *pipe_ctx); void hwss_program_output_csc(union block_sequence_params *params); -- 2.43.0