From: Wayne Lin <Wayne.Lin@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Harry Wentland <harry.wentland@amd.com>,
Leo Li <sunpeng.li@amd.com>,
Aurabindo Pillai <aurabindo.pillai@amd.com>,
Roman Li <roman.li@amd.com>, Wayne Lin <wayne.lin@amd.com>,
Tom Chung <chiahsuan.chung@amd.com>,
"Fangzhi Zuo" <jerry.zuo@amd.com>,
Dan Wheeler <daniel.wheeler@amd.com>, Ray Wu <Ray.Wu@amd.com>,
Ivan Lipski <ivan.lipski@amd.com>, Alex Hung <alex.hung@amd.com>,
James Lin <PingLei.Lin@amd.com>,
Chenyu Chen <Chen-Yu.Chen@amd.com>,
Tomasz Siemek <tomasz.siemek@amd.com>,
Alvin Lee <alvin.lee2@amd.com>
Subject: [PATCH 12/70] drm/amd/display: Refactor DPP_SET_OUTPUT_TRANSFER_FUNC to drop pipe_ctx
Date: Wed, 15 Jul 2026 21:37:22 +0800 [thread overview]
Message-ID: <20260715134432.1975118-13-Wayne.Lin@amd.com> (raw)
In-Reply-To: <20260715134432.1975118-1-Wayne.Lin@amd.com>
From: Tomasz Siemek <tomasz.siemek@amd.com>
[why]
Pipe_ctx shouldn't be passed as block sequence block parameter.
[how]
Adjust arguments for set_output_transfer_func and implementations.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Tomasz Siemek <tomasz.siemek@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
---
.../drm/amd/display/dc/core/dc_hw_sequencer.c | 50 ++++++++++++++-----
.../amd/display/dc/hwss/dce110/dce110_hwseq.c | 9 ++--
.../amd/display/dc/hwss/dce60/dce60_hwseq.c | 2 +-
.../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 11 ++--
.../amd/display/dc/hwss/dcn10/dcn10_hwseq.h | 3 +-
.../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 20 +++++---
.../amd/display/dc/hwss/dcn20/dcn20_hwseq.h | 3 +-
.../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 31 ++++++------
.../amd/display/dc/hwss/dcn30/dcn30_hwseq.h | 4 +-
.../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 31 ++++++------
.../amd/display/dc/hwss/dcn32/dcn32_hwseq.h | 8 ++-
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 22 ++++----
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.h | 4 +-
.../drm/amd/display/dc/hwss/hw_sequencer.h | 11 ++--
.../display/dc/hwss/hw_sequencer_private.h | 6 +--
15 files changed, 119 insertions(+), 96 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index 4f30d9ac4a0d..6002175420a0 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -1111,10 +1111,16 @@ void hwss_build_fast_sequence(struct dc *dc,
(*num_steps)++;
}
}
- if (hws->funcs.set_output_transfer_func && current_mpc_pipe->stream->update_flags.bits.out_tf) {
- block_sequence[*num_steps].params.set_output_transfer_func_params.dc = dc;
- block_sequence[*num_steps].params.set_output_transfer_func_params.pipe_ctx = current_mpc_pipe;
- block_sequence[*num_steps].params.set_output_transfer_func_params.stream = current_mpc_pipe->stream;
+ if (current_mpc_pipe->stream->update_flags.bits.out_tf) {
+ struct set_output_transfer_func_params *otf_params =
+ &block_sequence[*num_steps].params.set_output_transfer_func_params;
+
+ otf_params->dpp = current_mpc_pipe->plane_res.dpp;
+ otf_params->xfm = current_mpc_pipe->plane_res.xfm;
+ otf_params->mpc = dc->res_pool->mpc;
+ otf_params->mpcc_id = current_mpc_pipe->plane_res.hubp->inst;
+ otf_params->is_top_pipe = resource_is_pipe_type(pipe_ctx, OPP_HEAD);
+ otf_params->stream = current_mpc_pipe->stream;
block_sequence[*num_steps].func = DPP_SET_OUTPUT_TRANSFER_FUNC;
(*num_steps)++;
}
@@ -1271,9 +1277,7 @@ void hwss_execute_sequence(struct dc *dc,
hwss_program_manual_trigger(params);
break;
case DPP_SET_OUTPUT_TRANSFER_FUNC:
- hws->funcs.set_output_transfer_func(params->set_output_transfer_func_params.dc,
- params->set_output_transfer_func_params.pipe_ctx,
- params->set_output_transfer_func_params.stream);
+ hws->funcs.set_output_transfer_func(¶ms->set_output_transfer_func_params);
break;
case MPC_UPDATE_VISUAL_CONFIRM:
dc->hwss.update_visual_confirm_color(params->update_visual_confirm_params.dc,
@@ -1829,19 +1833,39 @@ void hwss_add_optc_program_manual_trigger(struct block_sequence_state *seq_state
* Helper function to add DPP set output transfer function to block sequence
*/
void hwss_add_dpp_set_output_transfer_func(struct block_sequence_state *seq_state,
- struct dc *dc,
- struct pipe_ctx *pipe_ctx,
- struct dc_stream_state *stream)
+ struct dc *dc, struct pipe_ctx *pipe_ctx)
{
if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
- seq_state->steps[*seq_state->num_steps].params.set_output_transfer_func_params.dc = dc;
- seq_state->steps[*seq_state->num_steps].params.set_output_transfer_func_params.pipe_ctx = pipe_ctx;
- seq_state->steps[*seq_state->num_steps].params.set_output_transfer_func_params.stream = stream;
+ seq_state->steps[*seq_state->num_steps].params.set_output_transfer_func_params =
+ (struct set_output_transfer_func_params) {
+ .xfm = pipe_ctx->plane_res.xfm,
+ .dpp = pipe_ctx->plane_res.dpp,
+ .mpc = dc->res_pool->mpc,
+ .mpcc_id = pipe_ctx->plane_res.hubp->inst,
+ .is_top_pipe = resource_is_pipe_type(pipe_ctx, OPP_HEAD),
+ .stream = pipe_ctx->stream,
+ };
seq_state->steps[*seq_state->num_steps].func = DPP_SET_OUTPUT_TRANSFER_FUNC;
(*seq_state->num_steps)++;
}
}
+void hwss_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx)
+{
+ if (dc->hwseq->funcs.set_output_transfer_func) {
+ dc->hwseq->funcs.set_output_transfer_func(
+ &(struct set_output_transfer_func_params) {
+ .xfm = pipe_ctx->plane_res.xfm,
+ .dpp = pipe_ctx->plane_res.dpp,
+ .mpc = dc->res_pool->mpc,
+ .mpcc_id = pipe_ctx->plane_res.hubp->inst,
+ .is_top_pipe = resource_is_pipe_type(pipe_ctx, OPP_HEAD),
+ .stream = pipe_ctx->stream,
+ }
+ );
+ }
+}
+
/*
* Helper function to add MPC update visual confirm to block sequence
*/
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index 74b046ab3bc3..4830a0d94177 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -607,11 +607,10 @@ dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
}
static bool
-dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
- const struct dc_stream_state *stream)
+dce110_set_output_transfer_func(struct set_output_transfer_func_params *params)
{
- (void)dc;
- struct transform *xfm = pipe_ctx->plane_res.xfm;
+ struct transform *xfm = params->xfm;
+ const struct dc_stream_state *stream = params->stream;
xfm->funcs->opp_power_on_regamma_lut(xfm, true);
xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
@@ -3181,7 +3180,7 @@ static void dce110_program_front_end_for_pipe(
hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
if (pipe_ctx->plane_state->update_bits.full_update)
- hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
+ hwss_set_output_transfer_func(dc, pipe_ctx);
DC_LOG_SURFACE(
"Pipe:%d %p: addr hi:0x%x, "
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
index 26aa303b8237..221996b348ab 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce60/dce60_hwseq.c
@@ -338,7 +338,7 @@ dce60_program_front_end_for_pipe(
hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
if (pipe_ctx->plane_state->update_bits.full_update)
- hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
+ hwss_set_output_transfer_func(dc, pipe_ctx);
DC_LOG_SURFACE(
"Pipe:%d %p: addr hi:0x%x, "
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
index 8c636698d6d4..3be0bde5aea1 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -2154,10 +2154,11 @@ static void log_tf(struct dc_context *ctx,
}
}
-bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
- const struct dc_stream_state *stream)
+bool dcn10_set_output_transfer_func(struct set_output_transfer_func_params *params)
{
- struct dpp *dpp = pipe_ctx->plane_res.dpp;
+ struct dpp *dpp = params->dpp;
+ const struct dc_stream_state *stream = params->stream;
+ struct dc *dc;
if (!stream)
return false;
@@ -2165,6 +2166,8 @@ bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
if (dpp == NULL)
return false;
+ dc = dpp->ctx->dc;
+
dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
if (stream->out_transfer_func.type == TF_TYPE_PREDEFINED &&
@@ -3301,7 +3304,7 @@ void dcn10_program_pipe(
* doing heavy calculation and programming
*/
if (pipe_ctx->plane_state->update_bits.full_update)
- hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
+ hwss_set_output_transfer_func(dc, pipe_ctx);
}
void dcn10_wait_for_pending_cleared(struct dc *dc,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h
index 162972dfdbe8..2cb674ba54e1 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h
@@ -73,8 +73,7 @@ void dcn10_program_output_csc(struct dc *dc,
enum dc_color_space colorspace,
uint16_t *matrix,
int opp_id);
-bool dcn10_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
- const struct dc_stream_state *stream);
+bool dcn10_set_output_transfer_func(struct set_output_transfer_func_params *params);
bool dcn10_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
const struct dc_plane_state *plane_state);
void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index 83794d5b838c..98778d5e114e 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -1019,26 +1019,30 @@ void dcn20_program_output_csc(struct dc *dc,
}
}
-bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
- const struct dc_stream_state *stream)
+bool dcn20_set_output_transfer_func(struct set_output_transfer_func_params *otf_params)
{
- int mpcc_id = pipe_ctx->plane_res.hubp->inst;
- struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
+ struct dpp *dpp = otf_params->dpp;
+ struct mpc *mpc = otf_params->mpc;
+ int mpcc_id = otf_params->mpcc_id;
+ bool is_top_pipe = otf_params->is_top_pipe;
+ const struct dc_stream_state *stream = otf_params->stream;
+ struct dc *dc = dpp->ctx->dc;
const struct pwl_params *params = NULL;
+
/*
* program OGAM only for the top pipe
* if there is a pipe split then fix diagnostic is required:
* how to pass OGAM parameter for stream.
* if programming for all pipes is required then remove condition
- * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic.
+ * is_top_pipe ,but then fix the diagnostic.
*/
if (mpc->funcs->power_on_mpc_mem_pwr)
mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
- if (pipe_ctx->top_pipe == NULL
+ if (is_top_pipe
&& mpc->funcs->set_output_gamma) {
if (stream->out_transfer_func.type == TF_TYPE_HWPWL)
params = &stream->out_transfer_func.pwl;
- else if (pipe_ctx->stream->out_transfer_func.type ==
+ else if (stream->out_transfer_func.type ==
TF_TYPE_DISTRIBUTED_POINTS &&
cm_helper_translate_curve_to_hw_format(dc->ctx,
&stream->out_transfer_func,
@@ -1991,7 +1995,7 @@ static void dcn20_program_pipe(
if (pipe_ctx->update_flags.bits.enable ||
pipe_ctx->update_flags.bits.plane_changed ||
pipe_ctx->stream->update_flags.bits.out_tf)
- hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
+ hwss_set_output_transfer_func(dc, pipe_ctx);
/* If the pipe has been enabled or has a different opp, we
* should reprogram the fmt. This deals with cases where
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h
index 9d1ad3b29ca5..749348d3c793 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h
@@ -44,8 +44,7 @@ void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
const struct dc_plane_state *plane_state);
-bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
- const struct dc_stream_state *stream);
+bool dcn20_set_output_transfer_func(struct set_output_transfer_func_params *params);
void dcn20_program_output_csc(struct dc *dc,
struct pipe_ctx *pipe_ctx,
enum dc_color_space colorspace,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
index 82a662efa49f..59184e146fc9 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
@@ -256,13 +256,10 @@ bool dcn30_set_blend_lut(
return result;
}
-static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx *pipe_ctx,
- const struct dc_stream_state *stream)
+static bool dcn30_set_mpc_shaper_3dlut(struct dpp *dpp, struct mpc *mpc,
+ int mpcc_id, const struct dc_stream_state *stream)
{
- struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
- int mpcc_id = pipe_ctx->plane_res.hubp->inst;
- struct dc *dc = pipe_ctx->stream->ctx->dc;
- struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
+ struct dc *dc = dpp->ctx->dc;
bool result = false;
uint32_t acquired_rmu = 0;
int mpcc_id_projected = 0;
@@ -274,8 +271,8 @@ static bool dcn30_set_mpc_shaper_3dlut(struct pipe_ctx *pipe_ctx,
shaper_lut = &stream->func_shaper->pwl;
} else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {
cm_helper_translate_curve_to_hw_format(stream->ctx, stream->func_shaper,
- &dpp_base->shaper_params, true);
- shaper_lut = &dpp_base->shaper_params;
+ &dpp->shaper_params, true);
+ shaper_lut = &dpp->shaper_params;
}
}
@@ -398,23 +395,25 @@ void dcn30_program_gamut_remap(struct program_gamut_remap_params *params)
mpc->funcs->set_gamut_remap(mpc, mpcc_id, &mpc_adjust);
}
-bool dcn30_set_output_transfer_func(struct dc *dc,
- struct pipe_ctx *pipe_ctx,
- const struct dc_stream_state *stream)
+bool dcn30_set_output_transfer_func(struct set_output_transfer_func_params *otf_params)
{
- int mpcc_id = pipe_ctx->plane_res.hubp->inst;
- struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
+ struct dpp *dpp = otf_params->dpp;
+ struct mpc *mpc = otf_params->mpc;
+ int mpcc_id = otf_params->mpcc_id;
+ bool is_top_pipe = otf_params->is_top_pipe;
+ const struct dc_stream_state *stream = otf_params->stream;
+ struct dc *dc = dpp->ctx->dc;
const struct pwl_params *params = NULL;
bool ret = false;
/* program OGAM or 3DLUT only for the top pipe*/
- if (pipe_ctx->top_pipe == NULL) {
+ if (is_top_pipe) {
/*program rmu shaper and 3dlut in MPC*/
- ret = dcn30_set_mpc_shaper_3dlut(pipe_ctx, stream);
+ ret = dcn30_set_mpc_shaper_3dlut(dpp, mpc, mpcc_id, stream);
if (ret == false && mpc->funcs->set_output_gamma) {
if (stream->out_transfer_func.type == TF_TYPE_HWPWL)
params = &stream->out_transfer_func.pwl;
- else if (pipe_ctx->stream->out_transfer_func.type ==
+ else if (stream->out_transfer_func.type ==
TF_TYPE_DISTRIBUTED_POINTS &&
cm3_helper_translate_curve_to_hw_format(stream->ctx,
&stream->out_transfer_func,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h
index 4182cf399424..0399642076eb 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h
@@ -65,9 +65,7 @@ bool dcn30_set_input_transfer_func(struct dc *dc,
void dcn30_program_gamut_remap(struct program_gamut_remap_params *params);
-bool dcn30_set_output_transfer_func(struct dc *dc,
- struct pipe_ctx *pipe_ctx,
- const struct dc_stream_state *stream);
+bool dcn30_set_output_transfer_func(struct set_output_transfer_func_params *params);
void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx);
void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index c2ea25927765..c5f6eb482f07 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -443,13 +443,10 @@ void dcn32_subvp_pipe_control_lock_fast(union block_sequence_params *params)
}
}
-bool dcn32_set_mpc_shaper_3dlut(
- struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream)
+bool dcn32_set_mpc_shaper_3dlut(struct dpp *dpp, struct mpc *mpc,
+ int mpcc_id, const struct dc_stream_state *stream)
{
- struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
- int mpcc_id = pipe_ctx->plane_res.hubp->inst;
- struct dc *dc = pipe_ctx->stream->ctx->dc;
- struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
+ struct dc *dc = dpp->ctx->dc;
bool result = false;
const struct pwl_params *shaper_lut = NULL;
@@ -460,8 +457,8 @@ bool dcn32_set_mpc_shaper_3dlut(
else if (stream->func_shaper->type == TF_TYPE_DISTRIBUTED_POINTS) {
cm_helper_translate_curve_to_hw_format(stream->ctx,
stream->func_shaper,
- &dpp_base->shaper_params, true);
- shaper_lut = &dpp_base->shaper_params;
+ &dpp->shaper_params, true);
+ shaper_lut = &dpp->shaper_params;
}
}
@@ -566,24 +563,24 @@ bool dcn32_set_input_transfer_func(struct dc *dc,
return result;
}
-bool dcn32_set_output_transfer_func(struct dc *dc,
- struct pipe_ctx *pipe_ctx,
- const struct dc_stream_state *stream)
+bool dcn32_set_output_transfer_func(struct set_output_transfer_func_params *otf_params)
{
- (void)dc;
- int mpcc_id = pipe_ctx->plane_res.hubp->inst;
- struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
+ struct dpp *dpp = otf_params->dpp;
+ struct mpc *mpc = otf_params->mpc;
+ int mpcc_id = otf_params->mpcc_id;
+ bool is_top_pipe = otf_params->is_top_pipe;
+ const struct dc_stream_state *stream = otf_params->stream;
const struct pwl_params *params = NULL;
bool ret = false;
/* program OGAM or 3DLUT only for the top pipe*/
- if (resource_is_pipe_type(pipe_ctx, OPP_HEAD)) {
+ if (is_top_pipe) {
/*program shaper and 3dlut in MPC*/
- ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream);
+ ret = dcn32_set_mpc_shaper_3dlut(dpp, mpc, mpcc_id, stream);
if (ret == false && mpc->funcs->set_output_gamma) {
if (stream->out_transfer_func.type == TF_TYPE_HWPWL)
params = &stream->out_transfer_func.pwl;
- else if (pipe_ctx->stream->out_transfer_func.type ==
+ else if (stream->out_transfer_func.type ==
TF_TYPE_DISTRIBUTED_POINTS &&
cm3_helper_translate_curve_to_hw_format(stream->ctx,
&stream->out_transfer_func,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
index 0303a5953673..090d94d38343 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h
@@ -54,12 +54,10 @@ bool dcn32_set_input_transfer_func(struct dc *dc,
struct pipe_ctx *pipe_ctx,
const struct dc_plane_state *plane_state);
-bool dcn32_set_mpc_shaper_3dlut(
- struct pipe_ctx *pipe_ctx, const struct dc_stream_state *stream);
+bool dcn32_set_mpc_shaper_3dlut(struct dpp *dpp_base, struct mpc *mpc,
+ int mpcc_id, const struct dc_stream_state *stream);
-bool dcn32_set_output_transfer_func(struct dc *dc,
- struct pipe_ctx *pipe_ctx,
- const struct dc_stream_state *stream);
+bool dcn32_set_output_transfer_func(struct set_output_transfer_func_params *params);
void dcn32_init_hw(struct dc *dc);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 5c1ba5d88c7a..161ef57ebce1 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -696,24 +696,24 @@ bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx,
return result;
}
-bool dcn401_set_output_transfer_func(struct dc *dc,
- struct pipe_ctx *pipe_ctx,
- const struct dc_stream_state *stream)
+bool dcn401_set_output_transfer_func(struct set_output_transfer_func_params *otf_params)
{
- (void)dc;
- int mpcc_id = pipe_ctx->plane_res.hubp->inst;
- struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
+ struct dpp *dpp = otf_params->dpp;
+ struct mpc *mpc = otf_params->mpc;
+ int mpcc_id = otf_params->mpcc_id;
+ bool is_top_pipe = otf_params->is_top_pipe;
+ const struct dc_stream_state *stream = otf_params->stream;
const struct pwl_params *params = NULL;
bool ret = false;
/* program OGAM or 3DLUT only for the top pipe*/
- if (resource_is_pipe_type(pipe_ctx, OPP_HEAD)) {
+ if (is_top_pipe) {
/*program shaper and 3dlut in MPC*/
- ret = dcn32_set_mpc_shaper_3dlut(pipe_ctx, stream);
+ ret = dcn32_set_mpc_shaper_3dlut(dpp, mpc, mpcc_id, stream);
if (ret == false && mpc->funcs->set_output_gamma) {
if (stream->out_transfer_func.type == TF_TYPE_HWPWL)
params = &stream->out_transfer_func.pwl;
- else if (pipe_ctx->stream->out_transfer_func.type ==
+ else if (stream->out_transfer_func.type ==
TF_TYPE_DISTRIBUTED_POINTS &&
cm3_helper_translate_curve_to_hw_format(stream->ctx,
&stream->out_transfer_func,
@@ -2397,7 +2397,7 @@ void dcn401_program_pipe(
if (pipe_ctx->update_flags.bits.enable ||
pipe_ctx->update_flags.bits.plane_changed ||
pipe_ctx->stream->update_flags.bits.out_tf)
- hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
+ hwss_set_output_transfer_func(dc, pipe_ctx);
/* If the pipe has been enabled or has a different opp, we
* should reprogram the fmt. This deals with cases where
@@ -2555,7 +2555,7 @@ void dcn401_program_pipe_sequence(
if (pipe_ctx->update_flags.bits.enable ||
pipe_ctx->update_flags.bits.plane_changed ||
pipe_ctx->stream->update_flags.bits.out_tf) {
- hwss_add_dpp_set_output_transfer_func(seq_state, dc, pipe_ctx, pipe_ctx->stream);
+ hwss_add_dpp_set_output_transfer_func(seq_state, dc, pipe_ctx);
}
/* If the pipe has been enabled or has a different opp, we
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
index 6d2e93149811..f90e25243ead 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
@@ -38,9 +38,7 @@ void dcn401_init_hw(struct dc *dc);
bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx,
const struct dc_plane_state *plane_state);
-bool dcn401_set_output_transfer_func(struct dc *dc,
- struct pipe_ctx *pipe_ctx,
- const struct dc_stream_state *stream);
+bool dcn401_set_output_transfer_func(struct set_output_transfer_func_params *params);
void dcn401_trigger_3dlut_dma_load(struct dc *dc,
struct pipe_ctx *pipe_ctx);
void dcn401_calculate_dccg_tmds_div_value(struct pipe_ctx *pipe_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
index d8398b39a119..e8bf96a7d63a 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
@@ -138,8 +138,11 @@ struct program_bias_and_scale_params {
};
struct set_output_transfer_func_params {
- struct dc *dc;
- struct pipe_ctx *pipe_ctx;
+ struct transform *xfm;
+ struct dpp *dpp;
+ struct mpc *mpc;
+ int mpcc_id;
+ bool is_top_pipe;
const struct dc_stream_state *stream;
};
@@ -1993,7 +1996,9 @@ void hwss_add_optc_program_manual_trigger(struct block_sequence_state *seq_state
struct pipe_ctx *pipe_ctx);
void hwss_add_dpp_set_output_transfer_func(struct block_sequence_state *seq_state,
- struct dc *dc, struct pipe_ctx *pipe_ctx, struct dc_stream_state *stream);
+ struct dc *dc, struct pipe_ctx *pipe_ctx);
+
+void hwss_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx);
void hwss_add_mpc_update_visual_confirm(struct block_sequence_state *seq_state,
struct dc *dc, struct pipe_ctx *pipe_ctx, int mpcc_id);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h
index b4956893ae9a..31ace62a37d9 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h
@@ -67,6 +67,8 @@ struct dc_phy_addr_space_config;
struct dc_virtual_addr_space_config;
struct hubp;
struct dpp;
+struct transform;
+struct mpc;
struct dce_hwseq;
struct timing_generator;
struct tg_color;
@@ -92,9 +94,7 @@ struct hwseq_private_funcs {
bool (*set_input_transfer_func)(struct dc *dc,
struct pipe_ctx *pipe_ctx,
const struct dc_plane_state *plane_state);
- bool (*set_output_transfer_func)(struct dc *dc,
- struct pipe_ctx *pipe_ctx,
- const struct dc_stream_state *stream);
+ bool (*set_output_transfer_func)(struct set_output_transfer_func_params *params);
void (*power_down)(struct dc *dc);
void (*enable_display_pipe_clock_gating)(struct dc_context *ctx,
bool clock_gating);
--
2.43.0
next prev parent reply other threads:[~2026-07-15 13:46 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-15 13:37 [PATCH 00/70] DC Patches July 13, 2026 Wayne Lin
2026-07-15 13:37 ` [PATCH 01/70] drm/amd/display: Correct pipe usage for populating stream config Wayne Lin
2026-07-15 13:37 ` [PATCH 02/70] drm/amd/display: Add Writeback Watermarks and Latency Fields Wayne Lin
2026-07-15 13:37 ` [PATCH 03/70] drm/amd/display: Add MCIF ARB programming structures Wayne Lin
2026-07-15 13:37 ` [PATCH 04/70] drm/amd/display: Increase HDMI AV mute wait from 2 to 3 frames Wayne Lin
2026-07-15 13:37 ` [PATCH 05/70] drm/amd/display: add dm_dmub_hw_init KUnit coverage Wayne Lin
2026-07-15 13:37 ` [PATCH 06/70] drm/amd/display: add dm_dmub_hw_resume " Wayne Lin
2026-07-15 13:37 ` [PATCH 07/70] drm/amd/display: add fused IO " Wayne Lin
2026-07-15 13:37 ` [PATCH 08/70] drm/amd/display: add DMUB command sync " Wayne Lin
2026-07-15 13:37 ` [PATCH 09/70] drm/amd/display: add VBIOS bounding box KUnit test Wayne Lin
2026-07-15 13:37 ` [PATCH 10/70] drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN4_2 from 3dlut code Wayne Lin
2026-07-15 13:37 ` [PATCH 11/70] drm/amd/display: Refactor DPP_PROGRAM_GAMUT_REMAP to drop pipe_ctx param Wayne Lin
2026-07-15 13:37 ` Wayne Lin [this message]
2026-07-15 13:37 ` [PATCH 13/70] drm/amd/display: Fix DP LT failure logging Wayne Lin
2026-07-15 13:37 ` [PATCH 14/70] drm/amd/display: Add updated MCIF ARB register definitions Wayne Lin
2026-07-15 13:37 ` [PATCH 15/70] drm/amd/display: Replace amdgpu_dm_kunit_helpers.h with dm_helpers.h Wayne Lin
2026-07-15 13:37 ` [PATCH 16/70] drm/amd/display: Add stream creation tests for connector Wayne Lin
2026-07-15 13:37 ` [PATCH 17/70] drm/amd/display: Add detect and poll " Wayne Lin
2026-07-15 13:37 ` [PATCH 18/70] drm/amd/display: Add register and unregister " Wayne Lin
2026-07-15 13:37 ` [PATCH 19/70] drm/amd/display: Add destroy " Wayne Lin
2026-07-15 13:37 ` [PATCH 20/70] drm/amd/display: Add encoder helper " Wayne Lin
2026-07-15 13:37 ` [PATCH 21/70] drm/amd/display: Add EDID management " Wayne Lin
2026-07-15 13:37 ` [PATCH 22/70] drm/amd/display: fix debug flags assignment in dmub_replay.c Wayne Lin
2026-07-15 13:37 ` [PATCH 23/70] drm/amd/display: Add DWB validation support to DML2.1 wrapper Wayne Lin
2026-07-15 13:37 ` [PATCH 24/70] drm/amd/display: Split DPMS ON into parts Wayne Lin
2026-07-15 13:37 ` [PATCH 25/70] drm/amd/display: Test color mod init and 3D LUT size Wayne Lin
2026-07-15 13:37 ` [PATCH 26/70] drm/amd/display: Test plane colorop helper walkers Wayne Lin
2026-07-15 13:37 ` [PATCH 27/70] drm/amd/display: Test CRTC color management update Wayne Lin
2026-07-15 13:37 ` [PATCH 28/70] drm/amd/display: Test plane " Wayne Lin
2026-07-15 13:37 ` [PATCH 29/70] drm/amd/display: Test plane colorop pipeline update Wayne Lin
2026-07-15 13:37 ` [PATCH 30/70] drm/amd/display: add KUnit tests for DM IP-block callbacks Wayne Lin
2026-07-15 13:37 ` [PATCH 31/70] drm/amd/display: add KUnit tests for DM CRTC vblank/scanout Wayne Lin
2026-07-15 13:37 ` [PATCH 32/70] drm/amd/display: add KUnit tests for DM atomic state helpers Wayne Lin
2026-07-15 13:37 ` [PATCH 33/70] drm/amd/display: add KUnit tests for DM stream scaling Wayne Lin
2026-07-15 13:37 ` [PATCH 34/70] drm/amd/display: add KUnit tests for HDCP state diffing Wayne Lin
2026-07-15 13:37 ` [PATCH 35/70] drm/amd/display: add KUnit tests for freesync config Wayne Lin
2026-07-15 13:37 ` [PATCH 36/70] drm/amd/display: add KUnit tests for per-frame master sync Wayne Lin
2026-07-15 13:37 ` [PATCH 37/70] drm/amd/display: add KUnit tests for stutter quirk Wayne Lin
2026-07-15 13:37 ` [PATCH 38/70] drm/amd/display: add KUnit tests for DPCD poweroff delay Wayne Lin
2026-07-15 13:37 ` [PATCH 39/70] drm/amd/display: add CRC source list KUnit coverage Wayne Lin
2026-07-15 13:37 ` [PATCH 40/70] drm/amd/display: add CRC source verify " Wayne Lin
2026-07-15 13:37 ` [PATCH 41/70] drm/amd/display: add CRC configure " Wayne Lin
2026-07-15 13:37 ` [PATCH 42/70] drm/amd/display: add CRC set-source " Wayne Lin
2026-07-15 13:37 ` [PATCH 43/70] drm/amd/display: add CRC IRQ handler " Wayne Lin
2026-07-15 13:37 ` [PATCH 44/70] drm/amd/display: Adjust the structure dml2_dchub_watermark_regs Wayne Lin
2026-07-15 13:37 ` [PATCH 45/70] drm/amd/display: Add mode helper tests for connector Wayne Lin
2026-07-15 13:37 ` [PATCH 46/70] drm/amd/display: Add i2c and EDID parsing " Wayne Lin
2026-07-15 13:37 ` [PATCH 47/70] drm/amd/display: Add mode validation and CEC " Wayne Lin
2026-07-15 13:37 ` [PATCH 48/70] drm/amd/display: Add stream validation " Wayne Lin
2026-07-15 13:37 ` [PATCH 49/70] drm/amd/display: Adjust structure dml2_display_dlg_regs Wayne Lin
2026-07-15 13:38 ` [PATCH 50/70] drm/amd/display: Revert Fix DMSS not triggering for HDR to SDR transition Wayne Lin
2026-07-15 13:38 ` [PATCH 51/70] drm/amd/display: Introduce dc_probe public object model Wayne Lin
2026-07-15 13:38 ` [PATCH 52/70] drm/amd/display: Introduce dc_update_state unified commit interface Wayne Lin
2026-07-15 13:38 ` [PATCH 53/70] drm/amd/display: Refactor dc_validation_set array into single root struct Wayne Lin
2026-07-15 13:38 ` [PATCH 54/70] drm/amd/display: Introduce dc_state_get_status unified status accessor Wayne Lin
2026-07-15 13:38 ` [PATCH 55/70] drm/amd/display: Introduce program_perfmon hwss hook and BLS perfmon sequence Wayne Lin
2026-07-15 13:38 ` [PATCH 56/70] drm/amd/display: Wire probe commit path into dc_update_state Wayne Lin
2026-07-15 13:38 ` [PATCH 57/70] drm/amd/display: Make dc_state_update const in commit path Wayne Lin
2026-07-15 13:38 ` [PATCH 58/70] drm/amd/display: Remove unused-but-set variable hubp from Wayne Lin
2026-07-15 13:38 ` [PATCH 59/70] drm/amd/display: set new_stream to NULL after release Wayne Lin
2026-07-15 13:38 ` [PATCH 60/70] drm/amd/display: Register DCN as a PMFW DF C-state client on DCN42 Wayne Lin
2026-07-15 13:38 ` [PATCH 61/70] drm/amd/display: fix wrong register field in dccg35_set_hdmistreamclk_src_new Wayne Lin
2026-07-15 13:38 ` [PATCH 62/70] drm/amd/display: wire DCN42B mcache programming callback Wayne Lin
2026-07-15 13:38 ` [PATCH 63/70] drm/amd/display: Trim DCE from DCN-only builds Wayne Lin
2026-07-15 13:38 ` [PATCH 64/70] drm/amd/display: hide Apple Studio Display secondary tile Wayne Lin
2026-07-15 13:38 ` [PATCH 65/70] drm/amd/display: Reduce DML reinitialization when params don't change Wayne Lin
2026-07-15 13:38 ` [PATCH 66/70] drm/amd/display: Add DCHUBBUB_HW_DEBUG offset/mask Wayne Lin
2026-07-15 13:38 ` [PATCH 67/70] drm/amd/display: Fix missing dc_3dlut forward declaration Wayne Lin
2026-07-15 13:38 ` [PATCH 68/70] drm/amd/display: Flush IRQ workqueue in schedule-work tests Wayne Lin
2026-07-15 15:38 ` McRae, Geoffrey
2026-07-15 13:38 ` [PATCH 69/70] drm/amd/display: Add SPL UPSP upsampling and YUV422 scaling support Wayne Lin
2026-07-15 13:38 ` [PATCH 70/70] drm/amd/display: Promote DC to 3.2.390 Wayne Lin
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