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Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC0.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPF8DEAB7A29 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Justin Chen Reverting this commit as it causes a regression lighting up eDP panels: This reverts commit 1fecc9989637 (drm/amd/display: Fix DMSS not triggering for HDR to SDR transition) Reviewed-by: Joshua Aberback Reviewed-by: Yihan Zhu Signed-off-by: Justin Chen Signed-off-by: Wayne Lin --- .../amd/display/dc/hwss/dce110/dce110_hwseq.c | 12 +++------- .../amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 21 +++++------------ .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 7 ++---- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 23 +++++-------------- .../drm/amd/display/modules/power/power_psr.c | 7 ------ .../amd/display/modules/power/power_replay.c | 7 ------ 6 files changed, 17 insertions(+), 60 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index 4830a0d94177..262982ca5ad9 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -1286,9 +1286,7 @@ void dce110_blank_stream(struct pipe_ctx *pipe_ctx) return; if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { - if (link->skip_implict_edp_power_control) - return; - if (hws) + if (!link->skip_implict_edp_power_control && hws) hws->funcs.edp_backlight_control(link, false); link->dc->hwss.set_abm_immediate_disable(pipe_ctx); } @@ -1794,9 +1792,7 @@ enum dc_status dce110_apply_single_controller_ctx_to_hw( dc->link_srv->set_dsc_enable(pipe_ctx, true); } - if (!stream->dpms_off && - !(link->connector_signal == SIGNAL_TYPE_EDP && - link->skip_implict_edp_power_control)) + if (!stream->dpms_off) dc->link_srv->set_dpms_on(context, pipe_ctx); /* DCN3.1 FPGA Workaround @@ -1815,9 +1811,7 @@ enum dc_status dce110_apply_single_controller_ctx_to_hw( * is constructed with the same sink). Make sure not to override * and link programming on the main. */ - if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM && - !(link->connector_signal == SIGNAL_TYPE_EDP && - link->skip_implict_edp_power_control)) { + if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) { pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false; pipe_ctx->stream->link->replay_settings.replay_feature_enabled = false; } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c index 6f1ad651ed2c..b6f3c0480ab6 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c @@ -537,11 +537,9 @@ static void dcn31_reset_back_end_for_pipe( } ASSERT(!pipe_ctx->top_pipe); - link = pipe_ctx->stream->link; + dc->hwss.set_abm_immediate_disable(pipe_ctx); - if (!(link->connector_signal == SIGNAL_TYPE_EDP && - link->skip_implict_edp_power_control)) - dc->hwss.set_abm_immediate_disable(pipe_ctx); + link = pipe_ctx->stream->link; if (dc->hwseq) dc->hwseq->wa_state.skip_blank_stream = false; @@ -557,11 +555,9 @@ static void dcn31_reset_back_end_for_pipe( pipe_ctx->stream_res.tg, OPTC_DSC_DISABLED, 0, 0); - if (!(link->connector_signal == SIGNAL_TYPE_EDP && - link->skip_implict_edp_power_control)) { - pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); - pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); - } + pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); + + pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) pipe_ctx->stream_res.tg->funcs->set_odm_bypass( pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); @@ -590,12 +586,7 @@ static void dcn31_reset_back_end_for_pipe( * screen only, the dpms_off would be true but * VBIOS lit up eDP, so check link status too. */ - if (link->connector_signal == SIGNAL_TYPE_EDP && - link->skip_implict_edp_power_control) { - /* DMSS is holding the panel across the commit; skip dpms-off. */ - if (pipe_ctx->stream_res.audio) - dc->hwss.disable_audio_stream(pipe_ctx); - } else if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) + if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) dc->link_srv->set_dpms_off(pipe_ctx); else if (pipe_ctx->stream_res.audio) dc->hwss.disable_audio_stream(pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index 4ed7480d1efa..f14c39a643da 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -1818,11 +1818,8 @@ void dcn35_disable_link_output(struct dc_link *link, disable_link_output_symclk_on_tx_off(link, DP_UNKNOWN_ENCODING); link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; } else { - if (!(signal == SIGNAL_TYPE_EDP && - link->skip_implict_edp_power_control)) { - link_hwss->disable_link_output(link, link_res, signal); - link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; - } + link_hwss->disable_link_output(link, link_res, signal); + link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; } /* * Add the logic to extract BOTH power up and power down sequences diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 161ef57ebce1..54afd42d73ed 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -1102,11 +1102,8 @@ void dcn401_disable_link_output(struct dc_link *link, disable_link_output_symclk_on_tx_off(link, DP_UNKNOWN_ENCODING); link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; } else { - if (!(signal == SIGNAL_TYPE_EDP && - link->skip_implict_edp_power_control)) { - link_hwss->disable_link_output(link, link_res, signal); - link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; - } + link_hwss->disable_link_output(link, link_res, signal); + link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; } if (signal == SIGNAL_TYPE_EDP && @@ -2154,12 +2151,7 @@ void dcn401_reset_back_end_for_pipe( * screen only, the dpms_off would be true but * VBIOS lit up eDP, so check link status too. */ - if (link->connector_signal == SIGNAL_TYPE_EDP && - link->skip_implict_edp_power_control) { - /* DMSS is holding the panel across the commit; skip dpms-off. */ - if (pipe_ctx->stream_res.audio) - dc->hwss.disable_audio_stream(pipe_ctx); - } else if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) + if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) dc->link_srv->set_dpms_off(pipe_ctx); else if (pipe_ctx->stream_res.audio) dc->hwss.disable_audio_stream(pipe_ctx); @@ -2184,15 +2176,12 @@ void dcn401_reset_back_end_for_pipe( * parent pipe. */ if (pipe_ctx->top_pipe == NULL) { - if (!(link->connector_signal == SIGNAL_TYPE_EDP && - link->skip_implict_edp_power_control)) { - dc->hwss.set_abm_immediate_disable(pipe_ctx); + dc->hwss.set_abm_immediate_disable(pipe_ctx); - pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); + pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); - pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); - } + pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) pipe_ctx->stream_res.tg->funcs->set_odm_bypass( pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); diff --git a/drivers/gpu/drm/amd/display/modules/power/power_psr.c b/drivers/gpu/drm/amd/display/modules/power/power_psr.c index 0ad4c4924696..5ecb570c204e 100644 --- a/drivers/gpu/drm/amd/display/modules/power/power_psr.c +++ b/drivers/gpu/drm/amd/display/modules/power/power_psr.c @@ -58,13 +58,6 @@ bool mod_power_psr_notify_mode_change(struct mod_power *mod_power, // stream_index is passed as validated parameter active_psr_events = core_power->map[stream_index].psr_events; - /* DMSS holds the panel in a forced PSR freeze (e.g. during HDR/SDR toggle). - * Re-running edp_setup_psr would reprogram DPCD 0x170 and disturb the freeze, - * so skip the PSR re-setup until DMSS releases the override. - */ - if (active_psr_events & psr_event_os_override_hold) - return false; - /* Calculate PSR configurations */ mod_power_calc_psr_configs(&psr_config, link, stream); diff --git a/drivers/gpu/drm/amd/display/modules/power/power_replay.c b/drivers/gpu/drm/amd/display/modules/power/power_replay.c index 1ad2ee01d560..e782501442c4 100644 --- a/drivers/gpu/drm/amd/display/modules/power/power_replay.c +++ b/drivers/gpu/drm/amd/display/modules/power/power_replay.c @@ -805,13 +805,6 @@ void mod_power_replay_notify_mode_change(struct mod_power *mod_power, core_power = MOD_POWER_TO_CORE(mod_power); active_replay_events = core_power->map[stream_index].replay_events; - /* DMSS holds the panel in a forced freeze (e.g. during HDR/SDR toggle). - * Re-running dp_setup_replay would reprogram DPCD 0x37B and disturb the - * freeze, so skip the replay re-setup until DMSS releases the override. - */ - if (active_replay_events & replay_event_os_override_hold) - return; - link->replay_settings.replay_smu_opt_enable = (link->replay_settings.config.replay_smu_opt_supported && mod_power_only_edp(dc->current_state, stream)); -- 2.43.0