Re: [PATCH 1/3] arm64: dts: qcom: ipq9574-rdp-common: Enable quad SPI mode for SPI-NAND

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [Medium] The device tree changes attempt to enable Quad SPI mode, but the underlying controller driver hardcodes single-bit transfers.
--

--- Patch [1]: [PATCH 1/3] arm64: dts: qcom: ipq9574-rdp-common: Enable quad SPI mode for SPI-NAND ---
commit fa94f9522a125598be3f36fef708de141603218d
Author: Md Sadre Alam <md.alam@oss.qualcomm.com>

arm64: dts: qcom: ipq9574-rdp-common: Enable quad SPI mode for SPI-NAND

This commit sets the SPI-NAND device node to use 4-bit transmit and
receive bus widths to enable quad SPI transfers.

> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
> index 62877b46f9b3f..86138529ba77e 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
> @@ -249,6 +249,8 @@ flash@0 {
>  		nand-ecc-engine = <&qpic_nand>;
>  		nand-ecc-strength = <4>;
>  		nand-ecc-step-size = <512>;
> +		spi-rx-bus-width = <4>;
> +		spi-tx-bus-width = <4>;

[Severity: Medium]
This is a pre-existing issue, but does enabling the 4-bit bus width here
actually result in quad SPI transfers?

Looking at the QPIC controller driver in drivers/spi/spi-qpic-snand.c,
qcom_spi_cmd_mapping() intercepts generic SPI NAND opcodes and hardcodes
SPI_TRANSFER_MODE_x1:

drivers/spi/spi-qpic-snand.c:qcom_spi_cmd_mapping() {
        ...
	case SPINAND_READ:
		if (snandc->qspi->raw_rw) {
			*cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
					SPI_WP | SPI_HOLD | OP_PAGE_READ);
		} else {
			*cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
					SPI_WP | SPI_HOLD | OP_PAGE_READ_WITH_ECC);
		}
        ...
}

It appears the driver completely ignores the bus widths negotiated by the
spi-mem framework, meaning transfers will silently remain single-bit.

Are there companion patches to the controller driver to handle the wider
bus widths, or is this device tree change ineffective on its own?

>  	};
>  };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260716-quad_dts-v1-0-74d86792944a@oss.qualcomm.com?part=1