From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4F3B2D6E64; Thu, 16 Jul 2026 13:54:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784210074; cv=none; b=DoFYpPPPxEZCYm2BIHWvrvTC9/oeOPaYACuU1QyE6ysNyAIj7Zyfgf1L0OJCWE6aJgXR32nVCIq6zb+L5KQAGXmZOghujAycpJMb/2eeQTacf3+SnZNlxQrBApDF50XmzAyDwn80ApLhubMegW+lWRGwqDLIJFGuzDEJgh2bVz4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784210074; c=relaxed/simple; bh=HKfnpHulevvJ2q64F4fIz4YV5x3Lz70Wgron2RHtHuA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=quVWQlAUfQN/ghNCm6u5JjC32lGjSlUrs4XzxQmQ93tJfD7RaDWT3YzulKm0m/3uwta7MASUh1XpRgmm3T7KjhbHOywUs+SU2vK9OXDJ3oB9Q5e2qpdl01fR3B5hl5Nr5ITwXh2IyDWraQrcy9JiyYESNRUEUb3XAPAvkSjKqVE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=HnD0Us3y; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="HnD0Us3y" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0CCF61F000E9; Thu, 16 Jul 2026 13:54:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1784210072; bh=wnlcSb0ipNe4LY1nKEeZ+6C1ilI8B4QvOX/UaOBdau0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=HnD0Us3y5MzQ2TRjlfvSA4AnLxG6FlswjHRvZLHtzS6mAobXFoiUXqIt7LfzC1fio 2pMbdbU4Yuj5V0jUXuV7jl52gn2bld87eYAE6Y/iJaMtAdmyyMCLPD9c36UafAoT/a sqwQb4aG+T0VGU1y1W+BBTvIHx6l4XqxILZeopF0= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Mark Rutland , Catalin Marinas , Fuad Tabba , James Morse , Marc Zyngier , Mark Brown , Oliver Upton , Vladimir Murzin , Will Deacon Subject: [PATCH 7.1 400/518] arm64: fpsimd: Fix type mismatch in sme_{save,load}_state() Date: Thu, 16 Jul 2026 15:31:08 +0200 Message-ID: <20260716133056.588467103@linuxfoundation.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260716133047.772246337@linuxfoundation.org> References: <20260716133047.772246337@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 7.1-stable review patch. If anyone has any objections, please let me know. ------------------ From: Mark Rutland commit 247bd153905085c18ff9006cca1ccb96dfd18e7f upstream. The sme_save_state() and sme_load_state() functions take a 32-bit int argument that describes whether to save/restore ZT0. Their assembly implementations consume the entire 64-bit register containing this 32-bit value, and will attempt to save/restore ZT0 if any bit of that 64-bit register is non-zero. Per the AAPCS64 parameter passing rules, the callee is responsible for any necessary widening, and the upper 32-bits are permitted to contain arbitrary values. If the upper 32 bits are non-zero, this could result in an unexpected attempt to save/restore ZT0, and consequently could lead to unexpected traps/undefs/faults. In practice compilers are very unlikely to generate code where the upper 32-bits would be non-zero, but they are permitted to do so. Fix this by only consuming the low 32 bits of the register, and update comments accordingly. Fixes: 95fcec713259 ("arm64/sme: Implement context switching for ZT0") Signed-off-by: Mark Rutland Cc: Catalin Marinas Cc: Fuad Tabba Cc: James Morse Cc: Marc Zyngier Cc: Mark Brown Cc: Oliver Upton Cc: Vladimir Murzin Cc: Will Deacon Cc: stable@vger.kernel.org Signed-off-by: Will Deacon Signed-off-by: Greg Kroah-Hartman --- arch/arm64/kernel/entry-fpsimd.S | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) --- a/arch/arm64/kernel/entry-fpsimd.S +++ b/arch/arm64/kernel/entry-fpsimd.S @@ -103,13 +103,13 @@ SYM_FUNC_END(sme_set_vq) * Save the ZA and ZT state * * x0 - pointer to buffer for state - * x1 - number of ZT registers to save + * w1 - number of ZT registers to save */ SYM_FUNC_START(sme_save_state) _sme_rdsvl 2, 1 // x2 = VL/8 sme_save_za 0, x2, 12 // Leaves x0 pointing to the end of ZA - cbz x1, 1f + cbz w1, 1f _str_zt 0 1: ret @@ -119,13 +119,13 @@ SYM_FUNC_END(sme_save_state) * Load the ZA and ZT state * * x0 - pointer to buffer for state - * x1 - number of ZT registers to save + * w1 - number of ZT registers to save */ SYM_FUNC_START(sme_load_state) _sme_rdsvl 2, 1 // x2 = VL/8 sme_load_za 0, x2, 12 // Leaves x0 pointing to the end of ZA - cbz x1, 1f + cbz w1, 1f _ldr_zt 0 1: ret