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Fri, 17 Jul 2026 08:46:11 +0000 From: Jamin Lin To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Kane Chen , Andrew Jeffery , Joel Stanley , Alistair Francis , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: Jamin Lin , Troy Lee , =?iso-8859-1?Q?C=E9dric_Le_Goater?= , =?iso-8859-1?Q?Philippe_Mathieu-Daud=E9?= Subject: [PATCH v4 8/9] hw/ssi/aspeed_smc: Add Data FIFO-based flash access support for AST2700 Thread-Topic: [PATCH v4 8/9] hw/ssi/aspeed_smc: Add Data FIFO-based flash access support for AST2700 Thread-Index: AQHdFci3q3btou94FE2nN3wpBynYPA== Date: Fri, 17 Jul 2026 08:46:11 +0000 Message-ID: <20260717084559.3477061-9-jamin_lin@aspeedtech.com> References: <20260717084559.3477061-1-jamin_lin@aspeedtech.com> In-Reply-To: <20260717084559.3477061-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; 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envelope-from=jamin_lin@aspeedtech.com; helo=TYPPR03CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org AST2700 supports a Data FIFO mode where flash accesses can be performed=0A= directly through Data FIFO MMIO offsets. The Data FIFO start offset=0A= increments by one for every 16MB of flash address space, allowing the=0A= chip select (CS) to be decoded from the Data FIFO offset.=0A= =0A= This change adds Data FIFO support to the Aspeed SMC model and introduces= =0A= a class callback to translate Data FIFO offsets into CS indices. For=0A= AST2700, the Data FIFO offset is matched against the segment start address= =0A= of each CS to determine the target flash device.=0A= =0A= The SMC register region size (nregs) is also extended dynamically=0A= based on the number of supported chip selects to cover all possible=0A= Data FIFO regions.=0A= =0A= This breaks migration compatibility with older QEMU builds for the=0A= affected models, even though Aspeed machines are not officially=0A= covered by migration compatibility guarantees.=0A= =0A= Bump version_id to 4 and minimum_version_id to 2 to reflect the=0A= incompatible format.=0A= =0A= Signed-off-by: Jamin Lin =0A= Reviewed-by: C=E9dric Le Goater =0A= Tested-by: Philippe Mathieu-Daud=E9 =0A= ---=0A= include/hw/ssi/aspeed_smc.h | 3 +-=0A= hw/ssi/aspeed_smc.c | 117 +++++++++++++++++++++++++++++++++---=0A= 2 files changed, 109 insertions(+), 11 deletions(-)=0A= =0A= diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h=0A= index a273365689..5f391fc24e 100644=0A= --- a/include/hw/ssi/aspeed_smc.h=0A= +++ b/include/hw/ssi/aspeed_smc.h=0A= @@ -47,7 +47,7 @@ struct AspeedSMCFlash {=0A= #define TYPE_ASPEED_SMC "aspeed.smc"=0A= OBJECT_DECLARE_TYPE(AspeedSMCState, AspeedSMCClass, ASPEED_SMC)=0A= =0A= -#define ASPEED_SMC_R_MAX (0x100 / 4)=0A= +#define ASPEED_SMC_R_MAX (0x300 / 4)=0A= #define ASPEED_SMC_CS_MAX 5=0A= =0A= struct AspeedSMCState {=0A= @@ -114,6 +114,7 @@ struct AspeedSMCClass {=0A= AspeedSegments *seg);=0A= void (*dma_ctrl)(AspeedSMCState *s, uint32_t value);=0A= int (*addr_width)(const AspeedSMCState *s);=0A= + int (*data_fifo_offset_to_cs)(const AspeedSMCState *s, uint32_t offset= );=0A= const MemoryRegionOps *reg_ops;=0A= };=0A= =0A= diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c=0A= index c8cc6cfa56..bf596f7b2d 100644=0A= --- a/hw/ssi/aspeed_smc.c=0A= +++ b/hw/ssi/aspeed_smc.c=0A= @@ -163,6 +163,9 @@=0A= /* Read Timing Compensation Register */=0A= #define R_TIMINGS (0x94 / 4)=0A= =0A= +/* Data fifo */=0A= +#define R_DATA_FIFO (0x200 / 4)=0A= +=0A= /* SPI controller registers and bits (AST2400) */=0A= #define R_SPI_CONF (0x00 / 4)=0A= #define SPI_CONF_ENABLE_W0 0=0A= @@ -209,6 +212,7 @@ static const AspeedSegments aspeed_2500_spi2_segments[]= ;=0A= #define ASPEED_SMC_FEATURE_DMA_GRANT 0x2=0A= #define ASPEED_SMC_FEATURE_WDT_CONTROL 0x4=0A= #define ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH 0x08=0A= +#define ASPEED_SMC_FEATURE_DATA_FIFO 0x10=0A= =0A= static inline bool aspeed_smc_has_dma(const AspeedSMCClass *asc)=0A= {=0A= @@ -225,6 +229,11 @@ static inline bool aspeed_smc_has_dma64(const AspeedSM= CClass *asc)=0A= return !!(asc->features & ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH);=0A= }=0A= =0A= +static inline bool aspeed_smc_has_data_fifo(const AspeedSMCClass *asc)=0A= +{=0A= + return !!(asc->features & ASPEED_SMC_FEATURE_DATA_FIFO);=0A= +}=0A= +=0A= #define aspeed_smc_error(fmt, ...) \= =0A= qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt "\n", __func__, ## __VA_ARGS= __)=0A= =0A= @@ -664,6 +673,7 @@ static MemTxResult aspeed_smc_read(void *opaque, hwaddr= addr, uint64_t *data,=0A= {=0A= AspeedSMCState *s =3D ASPEED_SMC(opaque);=0A= AspeedSMCClass *asc =3D ASPEED_SMC_GET_CLASS(opaque);=0A= + int cs;=0A= =0A= addr >>=3D 2;=0A= =0A= @@ -689,6 +699,18 @@ static MemTxResult aspeed_smc_read(void *opaque, hwadd= r addr, uint64_t *data,=0A= trace_aspeed_smc_read(addr << 2, size, s->regs[addr]);=0A= =0A= *data =3D s->regs[addr];=0A= + } else if (aspeed_smc_has_data_fifo(asc) && addr >=3D R_DATA_FIFO) {= =0A= + cs =3D asc->data_fifo_offset_to_cs(s, addr << 2);=0A= + if (cs >=3D 0) {=0A= + /*=0A= + * Data fifo mode only supports SPI user mode.=0A= + * The flash address is provided by the SPI command/address cy= cles,=0A= + * the MMIO addr parameter is ignored.=0A= + */=0A= + return aspeed_smc_flash_read(&s->flashes[cs], 0, data, size, a= ttrs);=0A= + }=0A= + aspeed_smc_error("Invalid data fifo offset %" HWADDR_PRIx, addr <<= 2);=0A= + return MEMTX_ERROR;=0A= } else {=0A= qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\= n",=0A= __func__, addr);=0A= @@ -1063,6 +1085,19 @@ static MemTxResult aspeed_smc_write(void *opaque, hw= addr addr, uint64_t data,=0A= } else if (aspeed_smc_has_dma(asc) && aspeed_smc_has_dma64(asc) &&=0A= addr =3D=3D R_DMA_DRAM_ADDR_HIGH) {=0A= s->regs[addr] =3D DMA_DRAM_ADDR_HIGH(value);=0A= + } else if (aspeed_smc_has_data_fifo(asc) && addr >=3D R_DATA_FIFO) {= =0A= + int cs =3D asc->data_fifo_offset_to_cs(s, addr << 2);=0A= + if (cs >=3D 0) {=0A= + /*=0A= + * Data fifo mode only supports SPI user mode.=0A= + * The flash address is provided by the SPI command/address cy= cles,=0A= + * the MMIO addr parameter is ignored.=0A= + */=0A= + return aspeed_smc_flash_write(&s->flashes[cs], 0, data, size,= =0A= + attrs);=0A= + }=0A= + aspeed_smc_error("Invalid data fifo offset %" HWADDR_PRIx, addr <<= 2);=0A= + return MEMTX_ERROR;=0A= } else {=0A= qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\= n",=0A= __func__, addr);=0A= @@ -1183,8 +1218,8 @@ static void aspeed_smc_realize(DeviceState *dev, Erro= r **errp)=0A= =0A= static const VMStateDescription vmstate_aspeed_smc =3D {=0A= .name =3D "aspeed.smc",=0A= - .version_id =3D 3,=0A= - .minimum_version_id =3D 1,=0A= + .version_id =3D 4,=0A= + .minimum_version_id =3D 2,=0A= .fields =3D (const VMStateField[]) {=0A= VMSTATE_UINT32_ARRAY(regs, AspeedSMCState, ASPEED_SMC_R_MAX),=0A= VMSTATE_UNUSED_V(2, 2), /* was snoop_index/snoop_dummies */=0A= @@ -1808,6 +1843,39 @@ static void aspeed_2700_smc_reg_to_segment(const Asp= eedSMCState *s,=0A= }=0A= }=0A= =0A= +/*=0A= + * Convert a data fifo offset to a chip select (CS).=0A= + *=0A= + * Data fifo access starts at 0x200. The data fifo offset index is=0A= + * calculated by subtracting the data fifo base offset from the MMIO addre= ss.=0A= + *=0A= + * The data fifo offset index increments by 1 for every 16MB of flash addr= ess=0A= + * space. Each offset step therefore represents a 16MB address decode rang= e.=0A= + *=0A= + * The CS is determined by matching the data fifo offset index against the= =0A= + * segment start address of each CS.=0A= + *=0A= + * Returns the CS index on success, or -1 if the offset is invalid.=0A= + */=0A= +static int aspeed_2700_smc_data_fifo_offset_to_cs(const AspeedSMCState *s,= =0A= + uint32_t offset)=0A= +{=0A= + AspeedSMCClass *asc =3D ASPEED_SMC_GET_CLASS(s);=0A= + uint32_t start_offset;=0A= + uint32_t fifo_offset;=0A= + int i;=0A= +=0A= + for (i =3D 0; i < asc->cs_num_max; i++) {=0A= + start_offset =3D (s->regs[R_SEG_ADDR0 + i] & 0x0000ffff) << 16;=0A= + fifo_offset =3D start_offset / 0x1000000;=0A= + if (fifo_offset =3D=3D offset - (R_DATA_FIFO << 2)) {=0A= + return i;=0A= + }=0A= + }=0A= +=0A= + return -1;=0A= +}=0A= +=0A= static const uint32_t aspeed_2700_fmc_resets[ASPEED_SMC_R_MAX] =3D {=0A= [R_CONF] =3D (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 |=0A= CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1),=0A= @@ -1842,6 +1910,27 @@ static const AspeedSegments aspeed_2700_fmc_segments= [] =3D {=0A= { 0x0, 0 }, /* disabled */=0A= };=0A= =0A= +/*=0A= + * AST2700 supports data fifo mode with a base data fifo start offset of 0= x200.=0A= + *=0A= + * The data fifo start offset increments by 1 for every 16MB of flash addr= ess=0A= + * space. Each offset step therefore represents a 16MB address decode rang= e.=0A= + *=0A= + * Assuming each chip select (CS) can use the maximum flash size of 256MB:= =0A= + * 256MB / 16MB =3D 0x10 offset steps per CS.=0A= + *=0A= + * Data fifo start offset for CSn:=0A= + * 0x200 + (n * 0x10)=0A= + *=0A= + * Examples:=0A= + * CS0: 0x200=0A= + * CS1: 0x210=0A= + * CS2: 0x220=0A= + * CS3: 0x230=0A= + *=0A= + * asc->nregs should be set to: 0x200 + (asc->cs_num_max * 0x10)=0A= + * to cover all possible data fifo regions.=0A= + */=0A= static void aspeed_2700_fmc_class_init(ObjectClass *klass, const void *dat= a)=0A= {=0A= DeviceClass *dc =3D DEVICE_CLASS(klass);=0A= @@ -1861,14 +1950,16 @@ static void aspeed_2700_fmc_class_init(ObjectClass = *klass, const void *data)=0A= asc->flash_window_base =3D 0x100000000;=0A= asc->flash_window_size =3D 1 * GiB;=0A= asc->features =3D ASPEED_SMC_FEATURE_DMA |=0A= - ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH;=0A= + ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH |=0A= + ASPEED_SMC_FEATURE_DATA_FIFO;=0A= asc->dma_flash_mask =3D 0x2FFFFFFC;=0A= asc->dma_dram_mask =3D 0xFFFFFFFC;=0A= asc->dma_start_length =3D 1;=0A= - asc->nregs =3D ASPEED_SMC_R_MAX;=0A= + asc->nregs =3D (0x200 + (asc->cs_num_max * 0x10)) >> 2;=0A= asc->segment_to_reg =3D aspeed_2700_smc_segment_to_reg;=0A= asc->reg_to_segment =3D aspeed_2700_smc_reg_to_segment;=0A= asc->dma_ctrl =3D aspeed_2600_smc_dma_ctrl;=0A= + asc->data_fifo_offset_to_cs =3D aspeed_2700_smc_data_fifo_offset_to_cs= ;=0A= asc->reg_ops =3D &aspeed_2700_smc_flash_ops;=0A= }=0A= =0A= @@ -1896,14 +1987,16 @@ static void aspeed_2700_spi0_class_init(ObjectClass= *klass, const void *data)=0A= asc->flash_window_base =3D 0x180000000;=0A= asc->flash_window_size =3D 1 * GiB;=0A= asc->features =3D ASPEED_SMC_FEATURE_DMA |=0A= - ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH;=0A= + ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH |=0A= + ASPEED_SMC_FEATURE_DATA_FIFO;=0A= asc->dma_flash_mask =3D 0x2FFFFFFC;=0A= asc->dma_dram_mask =3D 0xFFFFFFFC;=0A= asc->dma_start_length =3D 1;=0A= - asc->nregs =3D ASPEED_SMC_R_MAX;=0A= + asc->nregs =3D (0x200 + (asc->cs_num_max * 0x10)) >> 2;=0A= asc->segment_to_reg =3D aspeed_2700_smc_segment_to_reg;=0A= asc->reg_to_segment =3D aspeed_2700_smc_reg_to_segment;=0A= asc->dma_ctrl =3D aspeed_2600_smc_dma_ctrl;=0A= + asc->data_fifo_offset_to_cs =3D aspeed_2700_smc_data_fifo_offset_to_cs= ;=0A= asc->reg_ops =3D &aspeed_2700_smc_flash_ops;=0A= }=0A= =0A= @@ -1930,14 +2023,16 @@ static void aspeed_2700_spi1_class_init(ObjectClass= *klass, const void *data)=0A= asc->flash_window_base =3D 0x200000000;=0A= asc->flash_window_size =3D 1 * GiB;=0A= asc->features =3D ASPEED_SMC_FEATURE_DMA |=0A= - ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH;=0A= + ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH |=0A= + ASPEED_SMC_FEATURE_DATA_FIFO;=0A= asc->dma_flash_mask =3D 0x2FFFFFFC;=0A= asc->dma_dram_mask =3D 0xFFFFFFFC;=0A= asc->dma_start_length =3D 1;=0A= - asc->nregs =3D ASPEED_SMC_R_MAX;=0A= + asc->nregs =3D (0x200 + (asc->cs_num_max * 0x10)) >> 2;=0A= asc->segment_to_reg =3D aspeed_2700_smc_segment_to_reg;=0A= asc->reg_to_segment =3D aspeed_2700_smc_reg_to_segment;=0A= asc->dma_ctrl =3D aspeed_2600_smc_dma_ctrl;=0A= + asc->data_fifo_offset_to_cs =3D aspeed_2700_smc_data_fifo_offset_to_cs= ;=0A= asc->reg_ops =3D &aspeed_2700_smc_flash_ops;=0A= }=0A= =0A= @@ -1964,14 +2059,16 @@ static void aspeed_2700_spi2_class_init(ObjectClass= *klass, const void *data)=0A= asc->flash_window_base =3D 0x280000000;=0A= asc->flash_window_size =3D 1 * GiB;=0A= asc->features =3D ASPEED_SMC_FEATURE_DMA |=0A= - ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH;=0A= + ASPEED_SMC_FEATURE_DMA_DRAM_ADDR_HIGH |=0A= + ASPEED_SMC_FEATURE_DATA_FIFO;=0A= asc->dma_flash_mask =3D 0x0FFFFFFC;=0A= asc->dma_dram_mask =3D 0xFFFFFFFC;=0A= asc->dma_start_length =3D 1;=0A= - asc->nregs =3D ASPEED_SMC_R_MAX;=0A= + asc->nregs =3D (0x200 + (asc->cs_num_max * 0x10)) >> 2;=0A= asc->segment_to_reg =3D aspeed_2700_smc_segment_to_reg;=0A= asc->reg_to_segment =3D aspeed_2700_smc_reg_to_segment;=0A= asc->dma_ctrl =3D aspeed_2600_smc_dma_ctrl;=0A= + asc->data_fifo_offset_to_cs =3D aspeed_2700_smc_data_fifo_offset_to_cs= ;=0A= asc->reg_ops =3D &aspeed_2700_smc_flash_ops;=0A= }=0A= =0A= -- =0A= 2.43.0=0A=