All of lore.kernel.org
 help / color / mirror / Atom feed
From: sashiko-bot@kernel.org
To: "Dapeng Mi" <dapeng1.mi@linux.intel.com>
Cc: linux-perf-users@vger.kernel.org
Subject: Re: [Patch v3 8/8] perf/x86/intel: Prevent drain_pebs() reentry
Date: Fri, 17 Jul 2026 10:38:12 +0000	[thread overview]
Message-ID: <20260717103813.075C11F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260717080342.1879573-9-dapeng1.mi@linux.intel.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] TOCTOU race in intel_pmu_drain_bts_buffer leading to duplicate BTS records.
--

--- Patch [8]: [Patch v3 8/8] perf/x86/intel: Prevent drain_pebs() reentry ---
commit 77ebceadaa828dfb1bed75e560551cf29b1ae9f5
Author: Dapeng Mi <dapeng1.mi@linux.intel.com>

perf/x86/intel: Prevent drain_pebs() reentry

The PEBS buffer is shared by all events on a CPU, so drain_pebs() must
not run concurrently. This commit introduces __intel_pmu_quiesce() and
__intel_pmu_resume() helpers to disable the full PMU around the
drain_pebs() call, preventing reentry.

> diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
> index e86e4ba91e1b3..7f8b98d1837dc 100644
> --- a/arch/x86/events/intel/ds.c
> +++ b/arch/x86/events/intel/ds.c
> @@ -1240,13 +1240,6 @@ int intel_pmu_drain_bts_buffer(void)
>  	return 1;
>  }

[Severity: High]
This is a pre-existing issue, but since you are fixing the drain reentry 
race for PEBS, does intel_pmu_drain_bts_buffer() need similar protection?

If a user configures a BTS event alongside another active counter and 
disables the BTS event, the stop IPI can call this sequence without 
globally disabling the PMU:

__perf_event_stop()
  x86_pmu_stop()
    intel_pmu_disable_event()
      intel_pmu_drain_bts_buffer()

If a PMI interrupts execution precisely between reading the top pointer and 
resetting the index:

arch/x86/events/intel/ds.c:intel_pmu_drain_bts_buffer() {
    ...
    base = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
    top  = (struct bts_record *)(unsigned long)ds->bts_index;

    if (top <= base)
        return 0;

    memset(&regs, 0, sizeof(regs));

    <-- PMI FIRES HERE -->

    ds->bts_index = ds->bts_buffer_base;
    ...
}

Could the NMI handler unconditionally call intel_pmu_drain_bts_buffer(), 
draining the records and resetting the index, only for the interrupted 
context to resume and push the exact same records again using its stale 
top pointer?

Would it make sense to wrap the BTS draining logic with the newly 
introduced __intel_pmu_quiesce() and __intel_pmu_resume() helpers as well?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260717080342.1879573-1-dapeng1.mi@linux.intel.com?part=8

      reply	other threads:[~2026-07-17 10:38 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-17  8:03 [Patch v3 0/8] perf/x86: Miscellaneous PMU bug fixes and optimizations Dapeng Mi
2026-07-17  8:03 ` [Patch v3 1/8] perf/x86: Unregister PMI handler on PMU init failure Dapeng Mi
2026-07-17  8:33   ` sashiko-bot
2026-07-17  8:03 ` [Patch v3 2/8] perf/x86: Free hybrid state " Dapeng Mi
2026-07-17  8:03 ` [Patch v3 3/8] perf/x86: Guard intel_pmu_cpu_dead() against invalid hybrid PMU casts Dapeng Mi
2026-07-17  9:31   ` sashiko-bot
2026-07-17  8:03 ` [Patch v3 4/8] perf/x86/intel: Unwind cpuc state if PEBS buffer setup fails Dapeng Mi
2026-07-17  8:03 ` [Patch v3 5/8] perf/x86: Remove stale fixed counter helper and fix hybrid PMU access Dapeng Mi
2026-07-17  8:03 ` [Patch v3 6/8] perf/x86/intel: Fix intel_cap handling on hybrid PMUs Dapeng Mi
2026-07-17  8:03 ` [Patch v3 7/8] perf/x86: Optimize ACR handling in match_prev_assignment() Dapeng Mi
2026-07-17  8:03 ` [Patch v3 8/8] perf/x86/intel: Prevent drain_pebs() reentry Dapeng Mi
2026-07-17 10:38   ` sashiko-bot [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20260717103813.075C11F000E9@smtp.kernel.org \
    --to=sashiko-bot@kernel.org \
    --cc=dapeng1.mi@linux.intel.com \
    --cc=linux-perf-users@vger.kernel.org \
    --cc=sashiko-reviews@lists.linux.dev \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.