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From: sashiko-bot@kernel.org
To: "Luca Leonardo Scorcia" <l.scorcia@gmail.com>
Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org,
	robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH 7/7] soc: mediatek: mtk-mmsys: Add resets for mt8167
Date: Fri, 17 Jul 2026 15:30:52 +0000	[thread overview]
Message-ID: <20260717153053.225451F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260717151134.678839-8-l.scorcia@gmail.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Missing array mapping for MT8167_MMSYS_SW0_RST_B_MIPI_TX_CONFIG (ID 24) causes it to default to 0, unintentionally aliasing to and resetting the SMI_COMMON block.
--

--- Patch [7]: [PATCH 7/7] soc: mediatek: mtk-mmsys: Add resets for mt8167 ---
commit c0225a0e854c0cfee4ad1db37b9fac3a7690abdd
Author: Luca Leonardo Scorcia <l.scorcia@gmail.com>

soc: mediatek: mtk-mmsys: Add resets for mt8167

This commit adds 64 MMSYS resets for the MT8167 SoC, spanning two contiguous 
32-bit registers (SW0 and SW1).

> diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8167-mmsys.h
> index eef14083c47b5..b8f38ff8cf443 100644
> --- a/drivers/soc/mediatek/mt8167-mmsys.h
> +++ b/drivers/soc/mediatek/mt8167-mmsys.h
[ ... ]
> +/* MMSYS resets */
> +static const u8 mmsys_mt8167_rst_tb[] = {
> +	[MT8167_MMSYS_SW0_RST_B_SMI_COMMON]	= MMSYS_RST_NR(0, 0),
> +	[MT8167_MMSYS_SW0_RST_B_SMI_LARB0]	= MMSYS_RST_NR(0, 1),
[ ... ]
> +	[MT8167_MMSYS_SW0_RST_B_DSI0]		= MMSYS_RST_NR(0, 22),
> +	[MT8167_MMSYS_SW0_RST_B_DPI0]		= MMSYS_RST_NR(0, 23),
> +	/* bit 24 is SMI_COMMON again according to data sheet */
> +	/* bit 25 is SMI_LARB0 again according to data sheet */
> +	/* all other bits are not described in data sheet */
> +	[MT8167_MMSYS_SW1_RST_B_LVDS_ENCODER]	= MMSYS_RST_NR(1, 2),
> +	[MT8167_MMSYS_SW1_RST_B_DPI1]		= MMSYS_RST_NR(1, 3),
> +	[MT8167_MMSYS_SW1_RST_B_HDMI]		= MMSYS_RST_NR(1, 4),
> +};

[Severity: High]
Does this array omit the mapping for MT8167_MMSYS_SW0_RST_B_MIPI_TX_CONFIG
(ID 24)?

Because index 24 is unmapped in this array, it will default to 0. When a 
driver requests a reset for the MIPI TX config ID, mtk_mmsys_reset_update() 
will look up index 24 and retrieve 0, which directly maps to 
MMSYS_RST_NR(0, 0) (the SMI_COMMON block).

Can this omission cause the SMI_COMMON block to be unintentionally reset
instead, potentially disrupting the multimedia subsystem's memory transactions?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260717151134.678839-1-l.scorcia@gmail.com?part=7

      reply	other threads:[~2026-07-17 15:30 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-17 15:11 [PATCH 0/7] Properly describe mt8167 watchdog and mmsys resets Luca Leonardo Scorcia
2026-07-17 15:11 ` [PATCH 1/7] dt-bindings: reset: Add MT6589 toprgu reset IDs Luca Leonardo Scorcia
2026-07-17 15:25   ` sashiko-bot
2026-07-17 15:11 ` [PATCH 2/7] watchdog: mediatek: Add wdt/toprgu resets for MT6589 Luca Leonardo Scorcia
2026-07-17 15:11 ` [PATCH 3/7] dt-bindings: watchdog: Add compatible for MediaTek mt8167 Luca Leonardo Scorcia
2026-07-17 15:11 ` [PATCH 4/7] dt-bindings: reset: Add reset controller constants for mt8167 Luca Leonardo Scorcia
2026-07-17 15:11 ` [PATCH 5/7] watchdog: mediatek: Add support for mt8167 TOPRGU/WDT Luca Leonardo Scorcia
2026-07-17 15:11 ` [PATCH 6/7] arm64: dts: mt8167: Properly describe the SoC watchdog Luca Leonardo Scorcia
2026-07-17 15:11 ` [PATCH 7/7] soc: mediatek: mtk-mmsys: Add resets for mt8167 Luca Leonardo Scorcia
2026-07-17 15:30   ` sashiko-bot [this message]

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