Re: [PATCH v6 06/16] clk: qcom: qcm2290: Add RETAIN_FF_ENABLE flag for DISPCC and GPUCC GDSCs

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Hardware context retention failure due to conflicting SW_RESET flag in GPU GX GDSC.
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--- Patch [6]: [PATCH v6 06/16] clk: qcom: qcm2290: Add RETAIN_FF_ENABLE flag for DISPCC and GPUCC GDSCs ---
commit 190ef1fdcc32df401791889048619af17ae2bf71
Author: Imran Shaik <imran.shaik@oss.qualcomm.com>

clk: qcom: qcm2290: Add RETAIN_FF_ENABLE flag for DISPCC and GPUCC GDSCs

Add RETAIN_FF_ENABLE flag for DISPCC and GPUCC GDSCs on QCM2290 to retain
the register context across GDSC power collapse.

> diff --git a/drivers/clk/qcom/gpucc-qcm2290.c b/drivers/clk/qcom/gpucc-qcm2290.c
> index 3b130f69bb938..8d397cadc86aa 100644
> --- a/drivers/clk/qcom/gpucc-qcm2290.c
> +++ b/drivers/clk/qcom/gpucc-qcm2290.c

[ ... ]

> @@ -313,7 +313,7 @@ static struct gdsc gpu_gx_gdsc = {
>  	},
>  	.parent = &gpu_cx_gdsc.pd,
>  	.pwrsts = PWRSTS_OFF_ON,
> -	.flags = POLL_CFG_GDSCR | CLAMP_IO | AON_RESET | SW_RESET,
> +	.flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR | CLAMP_IO | AON_RESET | SW_RESET,

[Severity: High]
Does adding RETAIN_FF_ENABLE here conflict with the existing SW_RESET flag?

During runtime PM resume of the gpu_gx_gdsc domain, the GDSC framework calls
gdsc_enable(). Since SW_RESET is present, gdsc_enable() will call
gdsc_assert_reset() to pulse the block controller reset.

Won't this hardware reset immediately erase the flip-flop state that
RETAIN_FF_ENABLE was intended to preserve across power collapse?

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Sashiko AI review · https://sashiko.dev/#/patchset/20260718-shikra-dispcc-gpucc-v6-0-62703e05ef0f@oss.qualcomm.com?part=6