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DFC041F00A3A; Mon, 20 Jul 2026 01:26:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784510763; bh=8lR17PS+Su8iOHaA3iQrEy5VgOMzAQMSv3w+U50wEfo=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=gNoTGlOEcxuieLRgArLhEcNJl0gOUGkQNx64onWWtEna8aV9bvd9bwBrT4k9AO+MA Buunxi9VxqQAD7LX7frJ4FKEy+qRY7jWMBFmMPnSwE8a6K/LfD6kfZ9TrdULZkZ0H1 1p0bShqxkXr9FvnXQttMF+Y1HXmzKnBFhQ/j+IybWImb4/okh4SbzzTLs33vqm1i7n Uf/E6uO6eptnomDXwdD+EBCMBWRe4sFmQ2/pk8/V/6mnYcutDqg6q/eoNPPQ6/RSq9 dzk9aPzkNeUzbwcp6pXcl9CAmGAIyQ1jQrY0IWrmvmZyAeDSPPJdeKqG+zsNs0wJZP ULYuj75xRCvHQ== From: sashiko-bot@kernel.org Subject: Re: [PATCH v13 2/2] phy: qcom-mipi-csi2: Add a CSI2 MIPI DPHY driver To: =?utf-8?b?QnJ5YW4gTydEb25vZ2h1ZQ==?= Cc: media-ci@linuxtv.org, neil.armstrong@linaro.org, devicetree@vger.kernel.org, vkoul@kernel.org, olteanv@gmail.com, robh@kernel.org, linux-phy@lists.infradead.org, conor+dt@kernel.org In-Reply-To: <20260720-x1e-csi2-phy-v13-2-160c31958863@linaro.org> References: <20260720-x1e-csi2-phy-v13-0-160c31958863@linaro.org> <20260720-x1e-csi2-phy-v13-2-160c31958863@linaro.org> Date: Mon, 20 Jul 2026 01:26:02 +0000 Message-Id: <20260720012602.DFC041F00A3A@smtp.kernel.org> X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: sashiko-reviews@lists.linux.dev MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org VGhhbmsgeW91IGZvciB5b3VyIGNvbnRyaWJ1dGlvbiEgU2FzaGlrbyBBSSByZXZpZXcgZm91bmQg MiBwb3RlbnRpYWwgaXNzdWUocykgdG8gY29uc2lkZXI6Ci0gW0hpZ2hdIFZhbGlkIGNhbGN1bGF0 ZWQgc2V0dGxlX2NudCBvZiAwIGlzIHRyZWF0ZWQgYXMgYW4gZXJyb3IKLSBbTWVkaXVtXSBQb2xh cml0eSBjb25maWd1cmF0aW9uIG92ZXJ3cml0ZXMgdGhlIGVudGlyZSBDVFJMOSByZWdpc3RlciBp bnN0ZWFkIG9mIHVzaW5nIHJlYWQtbW9kaWZ5LXdyaXRlCi0tCgotLS0gUGF0Y2ggWzJdOiBbUEFU Q0ggdjEzIDIvMl0gcGh5OiBxY29tLW1pcGktY3NpMjogQWRkIGEgQ1NJMiBNSVBJIERQSFkgZHJp dmVyIC0tLQpjb21taXQgMWQyMWYwYjIzNjgwOGVjNjkwY2E0YmJkNWFjNjE5MGUyYzJjODczYgpB dXRob3I6IEJyeWFuIE8nRG9ub2dodWUgPGJyeWFuLm9kb25vZ2h1ZUBsaW5hcm8ub3JnPgpTdWJq ZWN0OiBwaHk6IHFjb20tbWlwaS1jc2kyOiBBZGQgYSBDU0kyIE1JUEkgRFBIWSBkcml2ZXIKCkFk ZCBhIG5ldyBNSVBJIENTSTIgZHJpdmVyIGluIERQSFkgbW9kZSBpbml0aWFsbHkuIFRoZSBlbnRp cmUgc2V0IG9mCmV4aXN0aW5nIENBTVNTIENTSSBQSFkgaW5pdCBzZXF1ZW5jZXMgYXJlIGltcG9y dGVkIGluIG9yZGVyIHRvIHNhdmUgdGltZQphbmQgZWZmb3J0IGluIGxhdGVyIHBhdGNoZXMuCgo+ IGRpZmYgLS1naXQgYS9kcml2ZXJzL3BoeS9xdWFsY29tbS9waHktcWNvbS1taXBpLWNzaTItM3Bo LWRwaHkuYyBiL2RyaXZlcnMvcGh5L3F1YWxjb21tL3BoeS1xY29tLW1pcGktY3NpMi0zcGgtZHBo eS5jCj4gbmV3IGZpbGUgbW9kZSAxMDA2NDQKPiAtLS0gL2Rldi9udWxsCj4gKysrIGIvZHJpdmVy cy9waHkvcXVhbGNvbW0vcGh5LXFjb20tbWlwaS1jc2kyLTNwaC1kcGh5LmMKWyAuLi4gXQo+ICtz dGF0aWMgaW50IHBoeV9xY29tX21pcGlfY3NpMl9sYW5lc19lbmFibGUoc3RydWN0IG1pcGlfY3Np MnBoeV9kZXZpY2UgKmNzaTJwaHksCj4gKwkJCQkJICAgc3RydWN0IG1pcGlfY3NpMnBoeV9zdHJl YW1fY2ZnICpjZmcpCj4gK3sKPiArCWNvbnN0IHN0cnVjdCBtaXBpX2NzaTJwaHlfZGV2aWNlX3Jl Z3MgKnJlZ3MgPSBjc2kycGh5X2Rldl90b19yZWdzKGNzaTJwaHkpOwo+ICsJc3RydWN0IG1pcGlf Y3NpMnBoeV9sYW5lc19jZmcgKmxhbmVfY2ZnID0gJmNmZy0+bGFuZV9jZmc7Cj4gKwl1OCBzZXR0 bGVfY250Owo+ICsJdTggdmFsOwo+ICsJaW50IGk7Cj4gKwo+ICsJaWYgKGNmZy0+bGlua19mcmVx IDw9IDApCj4gKwkJcmV0dXJuIC1FSU5WQUw7Cj4gKwo+ICsJc2V0dGxlX2NudCA9IHBoeV9xY29t X21pcGlfY3NpMl9zZXR0bGVfY250X2NhbGMoY2ZnLT5saW5rX2ZyZXEsIGNzaTJwaHktPnRpbWVy X2Nsa19yYXRlKTsKPiArCWlmICghc2V0dGxlX2NudCkKPiArCQlyZXR1cm4gLUVOT0RFVjsKCltT ZXZlcml0eTogSGlnaF0KU2hvdWxkIGEgcmV0dXJuIHZhbHVlIG9mIDAgZnJvbSBwaHlfcWNvbV9t aXBpX2NzaTJfc2V0dGxlX2NudF9jYWxjKCkgYmUKY29uc2lkZXJlZCB2YWxpZD8KCklmIHRoZSB0 aW1pbmcgcGFyYW1ldGVycyB5aWVsZCBleGFjdGx5IDYgZm9yIHRfaHNfc2V0dGxlX3BzIC8gdGlt ZXJfcGVyaW9kX3BzLAp0aGUgY2FsY3VsYXRpb24gZXZhbHVhdGVzIHRvIDAuIFRoaXMgdGhlbiBj YXVzZXMgdGhlIGxhbmUgZW5hYmxlIHNlcXVlbmNlIHRvCmZhaWwgaGVyZSB3aXRoIC1FTk9ERVYu CgpDb3VsZCBwaHlfcWNvbV9taXBpX2NzaTJfc2V0dGxlX2NudF9jYWxjKCkgcmV0dXJuIGEgbmVn YXRpdmUgZXJyb3IgY29kZSBmb3IKaW52YWxpZCB0aW1pbmdzIGluc3RlYWQgb2Ygb3ZlcmxvYWRp bmcgMCBhcyBhbiBlcnJvciB2YWx1ZT8KCj4gKwo+ICsJLyoKPiArCSAqIENTSV9DT01NT05fQ1RS TDUgaXMgYSBwaHlzaWNhbCBsYW5lIHBvd2VyLXVwIGJpdG1hcDoKPiArCSAqIC0gQml0cyBbMCwy LDQsNl0g4oaSIEQtUEhZIGRhdGEgbGFuZXMoTE4wLCBMTjIsIExONCwgTE42KQo+ICsJICogLSBC aXRzIFsxLDMsNV0g4oaSIEMtUEhZIHRyaW8gbGFuZXMoTE4xLCBMTjMsIExONSkKPiArCSAqIC0g Qml0IFs3XSDihpIgRC1QSFkgY2xvY2sgbGFuZShMTkNLKSBkZWRpY2F0ZWQgY2xvY2sgZW5hYmxl Cj4gKwkgKi8KPiArCXZhbCA9IEJJVChsYW5lX2NmZy0+Y2xrLnBvcyk7Cj4gKwlmb3IgKGkgPSAw OyBpIDwgY2ZnLT5udW1fZGF0YV9sYW5lczsgaSsrKQo+ICsJCXZhbCB8PSBCSVQobGFuZV9jZmct PmRhdGFbaV0ucG9zICogMik7Cj4gKwo+ICsJd3JpdGVsKHZhbCwgY3NpMnBoeS0+YmFzZSArCj4g KwkgICAgICAgQ1NJUEhZXzNQSF9DTU5fQ1NJX0NPTU1PTl9DVFJMbihyZWdzLT5jb21tb25fcmVn c19vZmZzZXQsIDUpKTsKPiArCj4gKwkvKiBMYW5lIGNvbmZpZ3VyYXRpb24gZm9yIHBvbGFyaXR5 IEAgQ1NJUEhZLWJhc2UgKyBDVFJMOSAqLwo+ICsJZm9yIChpID0gMDsgaSA8IGNmZy0+bnVtX2Rh dGFfbGFuZXM7IGkrKykgewo+ICsJCWlmIChsYW5lX2NmZy0+ZGF0YVtpXS5wb2wpIHsKPiArCQkJ dTggcG9zID0gbGFuZV9jZmctPmRhdGFbaV0ucG9zOwo+ICsKPiArCQkJd3JpdGVsKEJJVCgyKSwg Y3NpMnBoeS0+YmFzZSArIENTSVBIWV8yUEhfTE5fQ1NJXzJQSEFTRV9DVFJMOW4ocG9zICogMikp OwoKW1NldmVyaXR5OiBNZWRpdW1dCkRvZXMgdGhpcyB3cml0ZWwoKSB1bmludGVudGlvbmFsbHkg Y2xvYmJlciBvdGhlciBiaXRzIGluIHRoZQpDU0lQSFlfMlBIX0xOX0NTSV8yUEhBU0VfQ1RSTDlu IHJlZ2lzdGVyPwoKQSBkaXJlY3Qgd3JpdGUgb2YgQklUKDIpIHdpbGwgemVybyBvdXQgYWxsIG90 aGVyIGJpdHMgaW4gdGhlIHJlZ2lzdGVyLiBTaG91bGQKdGhpcyBiZSBhIHJlYWQtbW9kaWZ5LXdy aXRlIHNlcXVlbmNlIHRvIHByZXNlcnZlIGhhcmR3YXJlIGRlZmF1bHRzIG9yCmNhbGlicmF0aW9u cz8KCkFkZGl0aW9uYWxseSwgaWYgcG9sYXJpdHkgY29uZmlndXJhdGlvbiBpcyBkaXNhYmxlZCwg dGhlIHJlZ2lzdGVyIGlzIG5vdAp3cml0dGVuIGF0IGFsbCwgd2hpY2ggbWlnaHQgbGVhdmUgaXQg aW4gYW4gaW5jb25zaXN0ZW50IHN0YXRlIGlmIGl0IHdhcwpwcmV2aW91c2x5IG1vZGlmaWVkLgoK PiArCQl9Cj4gKwl9Cj4gKwo+ICsJaWYgKGxhbmVfY2ZnLT5jbGsucG9sKQo+ICsJCXdyaXRlbChC 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DFC041F00A3A; Mon, 20 Jul 2026 01:26:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784510763; bh=8lR17PS+Su8iOHaA3iQrEy5VgOMzAQMSv3w+U50wEfo=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=gNoTGlOEcxuieLRgArLhEcNJl0gOUGkQNx64onWWtEna8aV9bvd9bwBrT4k9AO+MA Buunxi9VxqQAD7LX7frJ4FKEy+qRY7jWMBFmMPnSwE8a6K/LfD6kfZ9TrdULZkZ0H1 1p0bShqxkXr9FvnXQttMF+Y1HXmzKnBFhQ/j+IybWImb4/okh4SbzzTLs33vqm1i7n Uf/E6uO6eptnomDXwdD+EBCMBWRe4sFmQ2/pk8/V/6mnYcutDqg6q/eoNPPQ6/RSq9 dzk9aPzkNeUzbwcp6pXcl9CAmGAIyQ1jQrY0IWrmvmZyAeDSPPJdeKqG+zsNs0wJZP ULYuj75xRCvHQ== From: sashiko-bot@kernel.org Subject: Re: [PATCH v13 2/2] phy: qcom-mipi-csi2: Add a CSI2 MIPI DPHY driver Reply-To: sashiko-reviews@lists.linux.dev To: =?utf-8?b?QnJ5YW4gTydEb25vZ2h1ZQ==?= Cc: media-ci@linuxtv.org, neil.armstrong@linaro.org, devicetree@vger.kernel.org, vkoul@kernel.org, olteanv@gmail.com, robh@kernel.org, linux-phy@lists.infradead.org, conor+dt@kernel.org In-Reply-To: <20260720-x1e-csi2-phy-v13-2-160c31958863@linaro.org> References: <20260720-x1e-csi2-phy-v13-0-160c31958863@linaro.org> <20260720-x1e-csi2-phy-v13-2-160c31958863@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Mon, 20 Jul 2026 01:26:02 +0000 Message-Id: <20260720012602.DFC041F00A3A@smtp.kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Thank you for your contribution! Sashiko AI review found 2 potential issue(= s) to consider: - [High] Valid calculated settle_cnt of 0 is treated as an error - [Medium] Polarity configuration overwrites the entire CTRL9 register inst= ead of using read-modify-write -- --- Patch [2]: [PATCH v13 2/2] phy: qcom-mipi-csi2: Add a CSI2 MIPI DPHY dr= iver --- commit 1d21f0b236808ec690ca4bbd5ac6190e2c2c873b Author: Bryan O'Donoghue Subject: phy: qcom-mipi-csi2: Add a CSI2 MIPI DPHY driver Add a new MIPI CSI2 driver in DPHY mode initially. The entire set of existing CAMSS CSI PHY init sequences are imported in order to save time and effort in later patches. > diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c b/drivers= /phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c > new file mode 100644 > --- /dev/null > +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c [ ... ] > +static int phy_qcom_mipi_csi2_lanes_enable(struct mipi_csi2phy_device *c= si2phy, > + struct mipi_csi2phy_stream_cfg *cfg) > +{ > + const struct mipi_csi2phy_device_regs *regs =3D csi2phy_dev_to_regs(csi= 2phy); > + struct mipi_csi2phy_lanes_cfg *lane_cfg =3D &cfg->lane_cfg; > + u8 settle_cnt; > + u8 val; > + int i; > + > + if (cfg->link_freq <=3D 0) > + return -EINVAL; > + > + settle_cnt =3D phy_qcom_mipi_csi2_settle_cnt_calc(cfg->link_freq, csi2p= hy->timer_clk_rate); > + if (!settle_cnt) > + return -ENODEV; [Severity: High] Should a return value of 0 from phy_qcom_mipi_csi2_settle_cnt_calc() be considered valid? If the timing parameters yield exactly 6 for t_hs_settle_ps / timer_period_= ps, the calculation evaluates to 0. This then causes the lane enable sequence to fail here with -ENODEV. Could phy_qcom_mipi_csi2_settle_cnt_calc() return a negative error code for invalid timings instead of overloading 0 as an error value? > + > + /* > + * CSI_COMMON_CTRL5 is a physical lane power-up bitmap: > + * - Bits [0,2,4,6] =E2=86=92 D-PHY data lanes(LN0, LN2, LN4, LN6) > + * - Bits [1,3,5] =E2=86=92 C-PHY trio lanes(LN1, LN3, LN5) > + * - Bit [7] =E2=86=92 D-PHY clock lane(LNCK) dedicated clock enable > + */ > + val =3D BIT(lane_cfg->clk.pos); > + for (i =3D 0; i < cfg->num_data_lanes; i++) > + val |=3D BIT(lane_cfg->data[i].pos * 2); > + > + writel(val, csi2phy->base + > + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, 5)); > + > + /* Lane configuration for polarity @ CSIPHY-base + CTRL9 */ > + for (i =3D 0; i < cfg->num_data_lanes; i++) { > + if (lane_cfg->data[i].pol) { > + u8 pos =3D lane_cfg->data[i].pos; > + > + writel(BIT(2), csi2phy->base + CSIPHY_2PH_LN_CSI_2PHASE_CTRL9n(pos * = 2)); [Severity: Medium] Does this writel() unintentionally clobber other bits in the CSIPHY_2PH_LN_CSI_2PHASE_CTRL9n register? A direct write of BIT(2) will zero out all other bits in the register. Shou= ld this be a read-modify-write sequence to preserve hardware defaults or calibrations? Additionally, if polarity configuration is disabled, the register is not written at all, which might leave it in an inconsistent state if it was previously modified. > + } > + } > + > + if (lane_cfg->clk.pol) > + writel(BIT(2), csi2phy->base + CSIPHY_2PH_LN_CSI_2PHASE_CTRL9n(lane_cf= g->clk.pos)); > + > + val =3D CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B; --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20260720-x1e-csi2-p= hy-v13-0-160c31958863@linaro.org?part=3D2