From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 201A2C44520 for ; Mon, 20 Jul 2026 15:27:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Reply-To:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: References:In-Reply-To:Cc:To:Subject:From:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=GDc3QYLivAtrGTbCAlqWaoChLG0ykptih3qCfvnCspM=; b=t9RNbkn7gHsFdO FeA1q/U87Q0iRXlA3Lb73mFlyyYL0zN1kzJ+5/kREbP4U3PCIc6gbWnCjflzAljsuJNb8pxWepT0A Gt6rWskji9gIWkktv/vmAYD+HEZS4PwAvKfMXYZ2Ntfepc87OqId41olhL/bT5aEwVZscgc2A6xEv /6iuzAanxRjYOahgg2OU4wOWe8wMxsR91VNrUwWBiuUiK6cxQUdvh6gxZRz7Q1bU2rYePWj8IzElS iJHp7Fl0MReIYUozbRjac9noWFzlaDorZHIswom8RmYSecDvDbHLEX+Rz1Y36fHl8+Vdcc9EcJKRy xew+G5n1fUWXmeya/tGQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wlptU-00000007BNw-3Foe; Mon, 20 Jul 2026 15:27:00 +0000 Received: from sea.source.kernel.org ([2600:3c0a:e001:78e:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wlptT-00000007BNL-13MZ for linux-amlogic@lists.infradead.org; Mon, 20 Jul 2026 15:26:59 +0000 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by sea.source.kernel.org (Postfix) with ESMTP id 078954133C; Mon, 20 Jul 2026 15:26:59 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7F6101F00A3A; Mon, 20 Jul 2026 15:26:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784561218; bh=NKMMf/o3lV9WryRPgZshT1tMeaccZ8lfExMbz1lt68g=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=M2/H/MXrKQFzMc+xl/qWN4r6E64csL6kzRTtp8tILKFtk8egLUGbtnE4PJHp6QHLL 9ZI28KrRIsXdO6RO0XyraZBrsRNarI0T4OFisjl6wJUhjqZsMT7xOmOlKGfOUL6NMT KLsPZHDyRJMR+mNnzXQwbecDJT8iyxi3iKtofScLT0KQvza18DNaioFW6B7UZSBUz8 hasdDKQyP+QHQsXmjsFaDrlHl6XUi/aBAGUCUm3Mtv/WhkeAvg++XTUaJK/Q0P4RyH pTuaRtiyOwly/DWFjj4eCoaDs6fNXMtVHYS231GM9mqh6Yxu6po4er16fvEUFRWR9l kFn2O4HIJKJ/A== From: sashiko-bot@kernel.org Subject: Re: [PATCH v3 08/16] PCI: dwc: fu740: Use cached PCIe capability offset To: "Hans Zhang" <18255117159@163.com> Cc: linux-amlogic@lists.infradead.org, linux-pci@vger.kernel.org, imx@lists.linux.dev, Frank.Li@kernel.org, neil.armstrong@linaro.org In-Reply-To: <20260720150619.24733-9-18255117159@163.com> References: <20260720150619.24733-1-18255117159@163.com> <20260720150619.24733-9-18255117159@163.com> Date: Mon, 20 Jul 2026 15:26:58 +0000 Message-Id: <20260720152658.7F6101F00A3A@smtp.kernel.org> X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: sashiko-reviews@lists.linux.dev MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org VGhhbmsgeW91IGZvciB5b3VyIGNvbnRyaWJ1dGlvbiEgU2FzaGlrbyBBSSByZXZpZXcgZm91bmQg MiBwb3RlbnRpYWwgaXNzdWUocykgdG8gY29uc2lkZXI6Ci0gW0NyaXRpY2FsXSBEV0MgZW5kcG9p bnQgY29yZSB1c2VzIHVuaW5pdGlhbGl6ZWQgYHBjaS0+cGNpZV9jYXBgIGR1cmluZyBzZXR1cCwg bGVhZGluZyB0byBzZXZlcmUgUENJIGNvbmZpZ3VyYXRpb24gc3BhY2UgY29ycnVwdGlvbi4KLSBb TG93XSBVbnVzZWQgdmFyaWFibGUgYGNhcGAgaW4gYGR3X3BjaWVfbGlua19nZXRfbWF4X2xpbmtf d2lkdGgoKWAsIGxlYWRpbmcgdG8gcmVkdW5kYW50IE1NSU8gcmVhZHMuCi0tCgotLS0gUGF0Y2gg WzhdOiBbUEFUQ0ggdjMgMDgvMTZdIFBDSTogZHdjOiBmdTc0MDogVXNlIGNhY2hlZCBQQ0llIGNh cGFiaWxpdHkgb2Zmc2V0IC0tLQpjb21taXQgMTg0YWE5Mjg1Yzk3YzI5ZjQxMjY1NmEzZTdmNjNh NTE1Mjg4ODEzYwpBdXRob3I6IEhhbnMgWmhhbmcgPDE4MjU1MTE3MTU5QDE2My5jb20+CgpQQ0k6 IGR3YzogZnU3NDA6IFVzZSBjYWNoZWQgUENJZSBjYXBhYmlsaXR5IG9mZnNldAoKVGhpcyBwYXRj aCBzZXJpZXMgdXBkYXRlcyB0aGUgRGVzaWduV2FyZSBQQ0llIGNvcmUgYW5kIHNldmVyYWwgY29u dHJvbGxlcgpkcml2ZXJzIHRvIGNhY2hlIHRoZSBQQ0llIGNhcGFiaWxpdHkgb2Zmc2V0LiBCeSBz dG9yaW5nIHRoZSBvZmZzZXQgaW4KcGNpLT5wY2llX2NhcCwgaXQgZWxpbWluYXRlcyB0aGUgbmVl ZCB0byByZXBlYXRlZGx5IHNlYXJjaCBmb3IgdGhlCmNhcGFiaWxpdHkgZHVyaW5nIGxpbmsgc2V0 dXAgYW5kIGluaXRpYWxpemF0aW9uLgoKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9wY2kvY29udHJv bGxlci9kd2MvcGNpZS1kZXNpZ253YXJlLWVwLmMgYi9kcml2ZXJzL3BjaS9jb250cm9sbGVyL2R3 Yy9wY2llLWRlc2lnbndhcmUtZXAuYwo+IGluZGV4IDdkMjc5NDk0NTcwNGUuLjE0MjI4YmU4YmJj ZTcgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9wY2kvY29udHJvbGxlci9kd2MvcGNpZS1kZXNpZ253 YXJlLWVwLmMKPiArKysgYi9kcml2ZXJzL3BjaS9jb250cm9sbGVyL2R3Yy9wY2llLWRlc2lnbndh cmUtZXAuYwo+IEBAIC0xMjQ2LDcgKzEyNDYsNyBAQCBzdGF0aWMgdm9pZCBkd19wY2llX2VwX2lu aXRfbm9uX3N0aWNreV9yZWdpc3RlcnMoc3RydWN0IGR3X3BjaWUgKnBjaSkKPiAgCSAqIHRvIGFs bCBvdGhlciBmdW5jdGlvbnMgYXMgd2VsbC4KPiAgCSAqLwo+ICAJaWYgKGZ1bmNzID4gMSkgewo+ IC0JCW9mZnNldCA9IGR3X3BjaWVfZmluZF9jYXBhYmlsaXR5KHBjaSwgUENJX0NBUF9JRF9FWFAp Owo+ICsJCW9mZnNldCA9IHBjaS0+cGNpZV9jYXA7CgpbU2V2ZXJpdHk6IENyaXRpY2FsXQpTaW5j ZSB0aGUgZ2VuZXJpYyBlbmRwb2ludCBpbml0aWFsaXphdGlvbiBwYXRoIG5ldmVyIGNhY2hlcyB0 aGUgY2FwYWJpbGl0eQpvZmZzZXQgKHVubGlrZSB0aGUgUm9vdCBDb21wbGV4IGluaXRpYWxpemF0 aW9uIHBhdGgpLCBkb2Vzbid0IHRoaXMgbWVhbgpwY2ktPnBjaWVfY2FwIHJlbWFpbnMgMD8KCklm IGl0IHJlbWFpbnMgMCwgdGhpcyBkaXJlY3QgYXNzaWdubWVudCB3aWxsIGNvcnJ1cHQgb2Zmc2V0 IDB4MEMgd2hlbgpyZWFkaW5nIGFuZCB3cml0aW5nIHRoZSBjYXBhYmlsaXR5LgoKRnVydGhlcm1v cmUsIGVhcmxpZXIgaW4gdGhpcyBmdW5jdGlvbjoKCmRyaXZlcnMvcGNpL2NvbnRyb2xsZXIvZHdj L3BjaWUtZGVzaWdud2FyZS1lcC5jOmR3X3BjaWVfZXBfaW5pdF9ub25fc3RpY2t5X3JlZ2lzdGVy cygpIHsKICAgIC4uLgogICAgZHdfcGNpZV9zZXR1cChwY2kpOwogICAgLi4uCn0KCkNhbGxpbmcg ZHdfcGNpZV9zZXR1cCgpIHVuY29uZGl0aW9uYWxseSBpbnZva2VzIGR3X3BjaWVfbGlua19zZXRf bWF4X3NwZWVkKCkKYW5kIGR3X3BjaWVfbGlua19zZXRfbWF4X2xpbmtfd2lkdGgoKS4gVGhlc2Ug ZnVuY3Rpb25zIG5vdyB1c2UgcGNpLT5wY2llX2NhcAp3aGljaCBldmFsdWF0ZXMgdG8gMCwgY2F1 c2luZyBzZXZlcmUgY29ycnVwdGlvbiBvZiBzdGFuZGFyZCBQQ0kgaGVhZGVyCnJlZ2lzdGVycyAo c3VjaCBhcyBIZWFkZXIgVHlwZSBhbmQgQ2FjaGUgTGluZSBTaXplIGF0IG9mZnNldCAweDBDKS4K Cj4gIAkJZnVuYzBfbG5rY2FwID0gZHdfcGNpZV9yZWFkbF9kYmkocGNpLCBvZmZzZXQgKyBQQ0lf RVhQX0xOS0NBUCk7Cj4gIAkJZnVuYzBfbG5rY2FwID0gRklFTERfR0VUKFBDSV9FWFBfTE5LQ0FQ X01MVyB8Cj4gIAkJCQkJIFBDSV9FWFBfTE5LQ0FQX1NMUywgZnVuYzBfbG5rY2FwKTsKClsgLi4u IF0KCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvcGNpL2NvbnRyb2xsZXIvZHdjL3BjaWUtZGVzaWdu d2FyZS5jIGIvZHJpdmVycy9wY2kvY29udHJvbGxlci9kd2MvcGNpZS1kZXNpZ253YXJlLmMKPiBp bmRleCBlYzQ3MjJlZDkzMDMyLi44MTA3MjliOTE4OTI4IDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMv cGNpL2NvbnRyb2xsZXIvZHdjL3BjaWUtZGVzaWdud2FyZS5jCj4gKysrIGIvZHJpdmVycy9wY2kv Y29udHJvbGxlci9kd2MvcGNpZS1kZXNpZ253YXJlLmMKClsgLi4uIF0KCj4gQEAgLTg0Myw3ICs4 NDIsNyBAQCBFWFBPUlRfU1lNQk9MX0dQTChkd19wY2llX3VwY29uZmlnX3NldHVwKTsKPiAgc3Rh dGljIHZvaWQgZHdfcGNpZV9saW5rX3NldF9tYXhfc3BlZWQoc3RydWN0IGR3X3BjaWUgKnBjaSkK PiAgewo+ICAJdTMyIGNhcCwgY3RybDIsIGxpbmtfc3BlZWQ7Cj4gLQl1OCBvZmZzZXQgPSBkd19w Y2llX2ZpbmRfY2FwYWJpbGl0eShwY2ksIFBDSV9DQVBfSURfRVhQKTsKPiArCXU4IG9mZnNldCA9 IHBjaS0+cGNpZV9jYXA7CgpbU2V2ZXJpdHk6IENyaXRpY2FsXQpXaGVuIGNhbGxlZCBmcm9tIHRo ZSBlbmRwb2ludCBpbml0aWFsaXphdGlvbiBwYXRoIHZpYSBkd19wY2llX3NldHVwKCksCmRvZXNu J3QgcGNpLT5wY2llX2NhcCBldmFsdWF0ZSB0byAwPwoKSWYgc28sIHRoaXMgYmFzZSBvZmZzZXQg cmVzb2x2ZXMgdG8gc3RhbmRhcmQgUENJIGhlYWRlciBieXRlcyBpbnN0ZWFkIG9mCnRoZSBQQ0ll IGNhcGFiaWxpdHkgcmVnaXN0ZXJzLCBjb3JydXB0aW5nIGNvbmZpZ3VyYXRpb24gc3BhY2Ugd2hl bgp3cml0aW5nIGJhY2sgdGhlIHVwZGF0ZWQgc3BlZWQgdmFsdWVzLgoKPiAgCj4gIAljYXAgPSBk d19wY2llX3JlYWRsX2RiaShwY2ksIG9mZnNldCArIFBDSV9FWFBfTE5LQ0FQKTsKPiAgCgpbIC4u LiBdCgo+IEBAIC04OTAsNyArODg5LDcgQEAgc3RhdGljIHZvaWQgZHdfcGNpZV9saW5rX3NldF9t YXhfc3BlZWQoc3RydWN0IGR3X3BjaWUgKnBjaSkKPiAgaW50IGR3X3BjaWVfbGlua19nZXRfbWF4 X2xpbmtfd2lkdGgoc3RydWN0IGR3X3BjaWUgKnBjaSkKPiAgewo+ICAJdTggY2FwID0gZHdfcGNp ZV9maW5kX2NhcGFiaWxpdHkocGNpLCBQQ0lfQ0FQX0lEX0VYUCk7Cj4gLQl1MzIgbG5rY2FwID0g ZHdfcGNpZV9yZWFkbF9kYmkocGNpLCBjYXAgKyBQQ0lfRVhQX0xOS0NBUCk7Cj4gKwl1MzIgbG5r Y2FwID0gZHdfcGNpZV9yZWFkbF9kYmkocGNpLCBwY2ktPnBjaWVfY2FwICsgUENJX0VYUF9MTktD QVApOwoKW1NldmVyaXR5OiBMb3ddCklzIHRoZSBjYXAgdmFyaWFibGUgc3RpbGwgbmVlZGVkIGhl cmU/IAoKSXQgc2VlbXMgdGhpcyBwZXJmb3JtcyBhIHJlZHVuZGFudCBNTUlPIHNlYXJjaCB2aWEg ZHdfcGNpZV9maW5kX2NhcGFiaWxpdHkoKQpidXQgdGhlIHJlc3VsdCBpcyBjb21wbGV0ZWx5IGln bm9yZWQgc2luY2UgdGhlIG5leHQgbGluZSBkaXJlY3RseSBhY2Nlc3NlcwpwY2ktPnBjaWVfY2Fw LgoKPiAgCj4gIAlyZXR1cm4gRklFTERfR0VUKFBDSV9FWFBfTE5LQ0FQX01MVywgbG5rY2FwKTsK PiAgfQoKWyAuLi4gXQoKPiBAQCAtOTM1LDEwICs5MzMsOSBAQCBzdGF0aWMgdm9pZCBkd19wY2ll X2xpbmtfc2V0X21heF9saW5rX3dpZHRoKHN0cnVjdCBkd19wY2llICpwY2ksIHUzMiBudW1fbGFu ZXMpCj4gIAlkd19wY2llX3dyaXRlbF9kYmkocGNpLCBQQ0lFX1BPUlRfTElOS19DT05UUk9MLCBw bGMpOwo+ICAJZHdfcGNpZV93cml0ZWxfZGJpKHBjaSwgUENJRV9MSU5LX1dJRFRIX1NQRUVEX0NP TlRST0wsIGx3c2MpOwo+ICAKPiAtCWNhcCA9IGR3X3BjaWVfZmluZF9jYXBhYmlsaXR5KHBjaSwg UENJX0NBUF9JRF9FWFApOwo+IC0JbG5rY2FwID0gZHdfcGNpZV9yZWFkbF9kYmkocGNpLCBjYXAg KyBQQ0lfRVhQX0xOS0NBUCk7Cj4gKwlsbmtjYXAgPSBkd19wY2llX3JlYWRsX2RiaShwY2ksIHBj aS0+cGNpZV9jYXAgKyBQQ0lfRVhQX0xOS0NBUCk7CgpbU2V2ZXJpdHk6IENyaXRpY2FsXQpTaW1p bGFyIHRvIGR3X3BjaWVfbGlua19zZXRfbWF4X3NwZWVkKCksIGlmIHRoaXMgaXMgY2FsbGVkIGZy b20gdGhlIGVuZHBvaW50CnNldHVwIHBhdGggd2hlcmUgcGNpLT5wY2llX2NhcCByZW1haW5zIHVu aW5pdGlhbGl6ZWQsIGRvZXNuJ3QgdGhpcyByZXN1bHQgaW4Kd3JpdGVzIHRvIHN0YW5kYXJkIFBD SSBoZWFkZXIgcmVnaXN0ZXJzIGluc3RlYWQgb2YgdGhlIFBDSWUgY2FwYWJpbGl0eT8KCj4gIAlG SUVMRF9NT0RJRlkoUENJX0VYUF9MTktDQVBfTUxXLCAmbG5rY2FwLCBudW1fbGFuZXMpOwo+IC0J ZHdfcGNpZV93cml0ZWxfZGJpKHBjaSwgY2FwICsgUENJX0VYUF9MTktDQVAsIGxua2NhcCk7Cj4g Kwlkd19wY2llX3dyaXRlbF9kYmkocGNpLCBwY2ktPnBjaWVfY2FwICsgUENJX0VYUF9MTktDQVAs IGxua2NhcCk7Cj4gIH0KCi0tIApTYXNoaWtvIEFJIHJldmlldyDCtyBodHRwczovL3Nhc2hpa28u ZGV2LyMvcGF0Y2hzZXQvMjAyNjA3MjAxNTA2MTkuMjQ3MzMtMS0xODI1NTExNzE1OUAxNjMuY29t P3BhcnQ9OAoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18K bGludXgtYW1sb2dpYyBtYWlsaW5nIGxpc3QKbGludXgtYW1sb2dpY0BsaXN0cy5pbmZyYWRlYWQu b3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtYW1s b2dpYwo= From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BEED30C606; Mon, 20 Jul 2026 15:26:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784561220; cv=none; b=nijz16wgWhQTfDgTNTqzR18EIATtI3z8xn039QSNhc8jEdnpuPI1Jh+HpcNjk1obJBPlHICLk5um9omVOR7wnSvDrY0Xse/TFVD8MzGs+bFmKm1ArlnxI7fBHbVEvpTsjIvQIcmI4+/Qh6ytL1ZIHAIC8N6iK/3e4g+gN6ggyvk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784561220; c=relaxed/simple; bh=OgaxjBhEa6Ca5r56R7HzvVcZBs0Y1Q787/QCUpRvqsk=; h=From:Subject:To:Cc:In-Reply-To:References:Content-Type:Date: Message-Id; b=Tk4dzCuquikh9+JBPMEW5gqS3CIN+GSksU/nH5NwzY+szMxMzTelGRq0W4r9yup7makC6DO9LiblMaf5S3kv3niF4G6B2EltzjtAXIH7SUD55/YWeLebORHnl8gjpB7jD7Xpimxc1eCV+XyS9iVQ+4323au8tRkY+KtTzzDYngs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=M2/H/MXr; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="M2/H/MXr" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7F6101F00A3A; Mon, 20 Jul 2026 15:26:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784561218; bh=NKMMf/o3lV9WryRPgZshT1tMeaccZ8lfExMbz1lt68g=; h=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date; b=M2/H/MXrKQFzMc+xl/qWN4r6E64csL6kzRTtp8tILKFtk8egLUGbtnE4PJHp6QHLL 9ZI28KrRIsXdO6RO0XyraZBrsRNarI0T4OFisjl6wJUhjqZsMT7xOmOlKGfOUL6NMT KLsPZHDyRJMR+mNnzXQwbecDJT8iyxi3iKtofScLT0KQvza18DNaioFW6B7UZSBUz8 hasdDKQyP+QHQsXmjsFaDrlHl6XUi/aBAGUCUm3Mtv/WhkeAvg++XTUaJK/Q0P4RyH pTuaRtiyOwly/DWFjj4eCoaDs6fNXMtVHYS231GM9mqh6Yxu6po4er16fvEUFRWR9l kFn2O4HIJKJ/A== From: sashiko-bot@kernel.org Subject: Re: [PATCH v3 08/16] PCI: dwc: fu740: Use cached PCIe capability offset Reply-To: sashiko-reviews@lists.linux.dev To: "Hans Zhang" <18255117159@163.com> Cc: linux-amlogic@lists.infradead.org, linux-pci@vger.kernel.org, imx@lists.linux.dev, Frank.Li@kernel.org, neil.armstrong@linaro.org In-Reply-To: <20260720150619.24733-9-18255117159@163.com> References: <20260720150619.24733-1-18255117159@163.com> <20260720150619.24733-9-18255117159@163.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Date: Mon, 20 Jul 2026 15:26:58 +0000 Message-Id: <20260720152658.7F6101F00A3A@smtp.kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Thank you for your contribution! Sashiko AI review found 2 potential issue(= s) to consider: - [Critical] DWC endpoint core uses uninitialized `pci->pcie_cap` during se= tup, leading to severe PCI configuration space corruption. - [Low] Unused variable `cap` in `dw_pcie_link_get_max_link_width()`, leadi= ng to redundant MMIO reads. -- --- Patch [8]: [PATCH v3 08/16] PCI: dwc: fu740: Use cached PCIe capability= offset --- commit 184aa9285c97c29f412656a3e7f63a515288813c Author: Hans Zhang <18255117159@163.com> PCI: dwc: fu740: Use cached PCIe capability offset This patch series updates the DesignWare PCIe core and several controller drivers to cache the PCIe capability offset. By storing the offset in pci->pcie_cap, it eliminates the need to repeatedly search for the capability during link setup and initialization. > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pc= i/controller/dwc/pcie-designware-ep.c > index 7d2794945704e..14228be8bbce7 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c > @@ -1246,7 +1246,7 @@ static void dw_pcie_ep_init_non_sticky_registers(st= ruct dw_pcie *pci) > * to all other functions as well. > */ > if (funcs > 1) { > - offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > + offset =3D pci->pcie_cap; [Severity: Critical] Since the generic endpoint initialization path never caches the capability offset (unlike the Root Complex initialization path), doesn't this mean pci->pcie_cap remains 0? If it remains 0, this direct assignment will corrupt offset 0x0C when reading and writing the capability. Furthermore, earlier in this function: drivers/pci/controller/dwc/pcie-designware-ep.c:dw_pcie_ep_init_non_sticky_= registers() { ... dw_pcie_setup(pci); ... } Calling dw_pcie_setup() unconditionally invokes dw_pcie_link_set_max_speed() and dw_pcie_link_set_max_link_width(). These functions now use pci->pcie_cap which evaluates to 0, causing severe corruption of standard PCI header registers (such as Header Type and Cache Line Size at offset 0x0C). > func0_lnkcap =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); > func0_lnkcap =3D FIELD_GET(PCI_EXP_LNKCAP_MLW | > PCI_EXP_LNKCAP_SLS, func0_lnkcap); [ ... ] > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/c= ontroller/dwc/pcie-designware.c > index ec4722ed93032..810729b918928 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c [ ... ] > @@ -843,7 +842,7 @@ EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup); > static void dw_pcie_link_set_max_speed(struct dw_pcie *pci) > { > u32 cap, ctrl2, link_speed; > - u8 offset =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > + u8 offset =3D pci->pcie_cap; [Severity: Critical] When called from the endpoint initialization path via dw_pcie_setup(), doesn't pci->pcie_cap evaluate to 0? If so, this base offset resolves to standard PCI header bytes instead of the PCIe capability registers, corrupting configuration space when writing back the updated speed values. > =20 > cap =3D dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); > =20 [ ... ] > @@ -890,7 +889,7 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie= *pci) > int dw_pcie_link_get_max_link_width(struct dw_pcie *pci) > { > u8 cap =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > - u32 lnkcap =3D dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); > + u32 lnkcap =3D dw_pcie_readl_dbi(pci, pci->pcie_cap + PCI_EXP_LNKCAP); [Severity: Low] Is the cap variable still needed here?=20 It seems this performs a redundant MMIO search via dw_pcie_find_capability() but the result is completely ignored since the next line directly accesses pci->pcie_cap. > =20 > return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap); > } [ ... ] > @@ -935,10 +933,9 @@ static void dw_pcie_link_set_max_link_width(struct d= w_pcie *pci, u32 num_lanes) > dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc); > dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc); > =20 > - cap =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > - lnkcap =3D dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); > + lnkcap =3D dw_pcie_readl_dbi(pci, pci->pcie_cap + PCI_EXP_LNKCAP); [Severity: Critical] Similar to dw_pcie_link_set_max_speed(), if this is called from the endpoint setup path where pci->pcie_cap remains uninitialized, doesn't this result in writes to standard PCI header registers instead of the PCIe capability? > FIELD_MODIFY(PCI_EXP_LNKCAP_MLW, &lnkcap, num_lanes); > - dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap); > + dw_pcie_writel_dbi(pci, pci->pcie_cap + PCI_EXP_LNKCAP, lnkcap); > } --=20 Sashiko AI review =C2=B7 https://sashiko.dev/#/patchset/20260720150619.2473= 3-1-18255117159@163.com?part=3D8