Re: [PATCH v7 2/6] arm64: dts: qcom: Add device tree for Nord GearVM variant

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Hardcoded GIC_ESPI interrupts in scmi57 through scmi63 conflict with apps_smmu_0.
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--- Patch [2]: [PATCH v7 2/6] arm64: dts: qcom: Add device tree for Nord GearVM variant ---
commit 1f36266e7d1bd796ddbb6d1dc183a6af6873f479
Author: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>

arm64: dts: qcom: Add device tree for Nord GearVM variant

This commit adds a SoC-level device tree include for the Nord GearVM variant
where a VM controls platform resources as an SCMI server. It includes shared
memory regions, QUPV3 GENI SE blocks, and a UFS host controller.

> diff --git a/arch/arm64/boot/dts/qcom/nord-gearvm.dtsi b/arch/arm64/boot/dts/qcom/nord-gearvm.dtsi
> new file mode 100644
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/nord-gearvm.dtsi

[ ... ]

> +	scmi57: scmi-57 {
> +		compatible = "qcom,scmi-smc";
> +		arm,smc-id = <0xc6008012>;
> +		shmem = <&shmem57>;
> +		interrupts = <GIC_ESPI 32 IRQ_TYPE_EDGE_RISING>;

[Severity: High]
Does this interrupt assignment conflict with apps_smmu_0?

The apps_smmu_0 node in the base nord.dtsi already claims GIC_ESPI 32 through
GIC_ESPI 127 using IRQ_TYPE_LEVEL_HIGH. Here, scmi57 through scmi63 are
sequentially assigned GIC_ESPI 32 through GIC_ESPI 38 with
IRQ_TYPE_EDGE_RISING.

The kernel IRQ subsystem strictly prohibits sharing interrupts with mismatched
trigger types. This will cause request_irq() to fail for whichever driver
probes second. Because apps_smmu_0 acts as the IOMMU for core peripherals,
and SCMI controls critical power domains, a probe failure here might leave
core subsystems unpowered or unbootable.

> +		interrupt-names = "a2p";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		arm,max-msg = <10>;
> +		arm,max-msg-size = <256>;
> +		arm,max-rx-timeout-ms = <3000>;

[ ... ]

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Sashiko AI review · https://sashiko.dev/#/patchset/20260721044005.2882803-1-shengchao.guo@oss.qualcomm.com?part=2