Re: [PATCH v2 2/2] iio: magnetometer: add support for QST QMC6308

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Potential hardware initialization race condition during soft reset deassertion.
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--- Patch [2]: [PATCH v2 2/2] iio: magnetometer: add support for QST QMC6308 ---
commit 50ae109e19c53c095dd871b420a64fb846f258d5
Author: Jorijn van der Graaf <jorijnvdgraaf@catcrafts.net>

iio: magnetometer: add support for QST QMC6308

This commit adds support for the QST QMC6308 3-axis anisotropic
magnetoresistive magnetometer on I2C. It implements raw readings, output
data rate, field range, filter oversampling ratio, mount matrix, and
runtime PM.

> diff --git a/drivers/iio/magnetometer/qmc6308.c b/drivers/iio/magnetometer/qmc6308.c
> new file mode 100644
> index 0000000000000..7d4df846bbc54
> --- /dev/null
> +++ b/drivers/iio/magnetometer/qmc6308.c
[ ... ]
> +static int qmc6308_init(struct qmc6308_data *data)
> +{
[ ... ]
> +	/* The SOFT_RST bit is not auto-cleared and must be written back 0 */
> +	ret = regmap_write(map, QMC6308_REG_CTRL2, QMC6308_SOFT_RST);
> +	if (ret)
> +		return ret;
> +
> +	/*
> +	 * The datasheet gives no soft-reset completion figure; reuse the
> +	 * power-on time as a conservative bound.
> +	 */
> +	fsleep(QMC6308_POR_US);
> +
> +	data->range = QMC6308_RNG_30G;
> +	data->odr = QMC6308_ODR_50HZ;
> +	data->osr = QMC6308_OSR1_8;
> +
> +	ret = regmap_write(map, QMC6308_REG_CTRL2,
> +			   FIELD_PREP(QMC6308_SET_RESET_MASK,
> +				      QMC6308_SET_RESET_ON) |
> +			   FIELD_PREP(QMC6308_RNG_MASK, data->range));
> +	if (ret)
> +		return ret;
> +
> +	/* OSR2 (second-stage filter) set to its power-on default of 0 */
> +	return regmap_write(map, QMC6308_REG_CTRL1,

[Severity: Medium]
If the soft reset logic is level-sensitive and holds the chip in reset while
the bit is 1, the initialization occurs only after the bit is cleared to 0 by
the second write to QMC6308_REG_CTRL2.

Can the hardware reliably accept this immediate subsequent write to
QMC6308_REG_CTRL1 without any delay, or does it need time to initialize after
the reset is deasserted?

> +			    FIELD_PREP(QMC6308_MODE_MASK,
> +				       QMC6308_MODE_NORMAL) |
> +			    FIELD_PREP(QMC6308_ODR_MASK, data->odr) |
> +			    FIELD_PREP(QMC6308_OSR1_MASK, data->osr) |
> +			    FIELD_PREP(QMC6308_OSR2_MASK, 0));
> +}

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Sashiko AI review · https://sashiko.dev/#/patchset/20260721134843.7484-1-jorijnvdgraaf@catcrafts.net?part=2