From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D073A415F16; Tue, 21 Jul 2026 20:13:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784664823; cv=none; b=ceUtShRdr/fK3QVorGyLBBAgw77ezCEkdWV8qrJPwGG6ube3y8OHoTbahvtqQAWqjEY4Oev2DOp1XvPkJuXhlukx8lBotZKeNnBf7m+J9CkwIXjFQtS2yBRMsi/r0DpfEhSXMuTY6Yo85O3JoTx9NlQ9XzXKYMBIjUpQA5mx8xE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784664823; c=relaxed/simple; bh=bagHkSV4DpNqqij7cfJeWTMfEmVQTxENr7s0QKj7Tbo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XxChI+XdM5psAG2H11MM1SXgxC1cScBijkcoGo7Z4IjDdctcwT91oCit4ANFTOqSdG8gTuSv6S1xkoNCcPLkjLrq7LAs+uCYEw3MpKBN08Xm3/O0rST3L+Kl9YOpsixH1y7/Yx30k9OkYqKBjICxW1qyG8oj6Nlvi61+HfOx2t0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=g+FttY+p; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="g+FttY+p" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 477661F00A3D; Tue, 21 Jul 2026 20:13:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1784664822; bh=7/OSFbHWV1zVvaYIw8CkcPfjVkBPcSx+ZDcXGX8/04w=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=g+FttY+pVzf8pAp8rOg/Urn0/BEFnhoBFRZXyqphc1BySc4FSt4EXSXn+3u97dX5L 9uchKrOQe40RIoOhhXHdvFiwA6ptnv6zzAuOl34nW6kUZfsvrNI7V58hTBQKq6zTYA Z4hjBrw9W3QvDQXA+i3mFss5050HWuPu3/xTzfGI= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Suzuki K Poulose , Marc Zyngier , Catalin Marinas , Oliver Upton , Colton Lewis , Sasha Levin Subject: [PATCH 6.6 0071/1266] arm64: Treat HCR_EL2.E2H as RES1 when ID_AA64MMFR4_EL1.E2H0 is negative Date: Tue, 21 Jul 2026 17:08:28 +0200 Message-ID: <20260721152443.389547224@linuxfoundation.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260721152441.786066624@linuxfoundation.org> References: <20260721152441.786066624@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.6-stable review patch. If anyone has any objections, please let me know. ------------------ From: Marc Zyngier [ Upstream commit 3944382fa6f22b54fd399632b1af92c28123979b ] For CPUs that have ID_AA64MMFR4_EL1.E2H0 as negative, it is important to avoid the boot path that sets HCR_EL2.E2H=0. Fortunately, we already have this path to cope with fruity CPUs. Tweak init_el2 to look at ID_AA64MMFR4_EL1.E2H0 first. Reviewed-by: Suzuki K Poulose Signed-off-by: Marc Zyngier Reviewed-by: Catalin Marinas Link: https://lore.kernel.org/r/20240122181344.258974-8-maz@kernel.org Signed-off-by: Oliver Upton Signed-off-by: Colton Lewis Signed-off-by: Sasha Levin --- arch/arm64/kernel/head.S | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index 6517bf2644a08b..e32c8dd0b17a77 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -589,25 +589,32 @@ SYM_INNER_LABEL(init_el2, SYM_L_LOCAL) mov_q x1, INIT_SCTLR_EL1_MMU_OFF /* - * Fruity CPUs seem to have HCR_EL2.E2H set to RES1, - * making it impossible to start in nVHE mode. Is that - * compliant with the architecture? Absolutely not! + * Compliant CPUs advertise their VHE-onlyness with + * ID_AA64MMFR4_EL1.E2H0 < 0. HCR_EL2.E2H can be + * RES1 in that case. + * + * Fruity CPUs seem to have HCR_EL2.E2H set to RES1, but + * don't advertise it (they predate this relaxation). */ + mrs_s x0, SYS_ID_AA64MMFR4_EL1 + ubfx x0, x0, #ID_AA64MMFR4_EL1_E2H0_SHIFT, #ID_AA64MMFR4_EL1_E2H0_WIDTH + tbnz x0, #(ID_AA64MMFR4_EL1_E2H0_SHIFT + ID_AA64MMFR4_EL1_E2H0_WIDTH - 1), 1f + mrs x0, hcr_el2 and x0, x0, #HCR_E2H - cbz x0, 1f - + cbz x0, 2f +1: /* Set a sane SCTLR_EL1, the VHE way */ pre_disable_mmu_workaround msr_s SYS_SCTLR_EL12, x1 mov x2, #BOOT_CPU_FLAG_E2H - b 2f + b 3f -1: +2: pre_disable_mmu_workaround msr sctlr_el1, x1 mov x2, xzr -2: +3: __init_el2_nvhe_prepare_eret mov w0, #BOOT_CPU_MODE_EL2 -- 2.53.0