From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 150B2431A5C; Tue, 21 Jul 2026 19:22:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784661731; cv=none; b=d0cz3GpirSlZidIW5kP1OsMwLlwXhxmpd7bqWkKo+sN6c/sBBwYII5w1Y7lfdfrWjfnLvMI2apWpG9cGgFvgKXJTeDJHhT59jk/A95AW2hOyTJK/mbwm5tCgh+PM9FowU++81FIMOVUdT53q4MVnx0sfTg3ZGtCRUYO6MS7CPWw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784661731; c=relaxed/simple; bh=rTSFhI1y2Im9VEUR7TmwHpHI8m6I8EtNkac8WOxxk9Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aBEsxWi3qF1yjkepv5EjewoD8pL7RoJXdj7+jY/bJODjRVnKZX80kFRrqKFgVn7RLqN0mQTGuaefeRXVG/378cS6pkeNheyx4tVattb3c5ln47j/Br6V+O7nz2kTLTKYhNsAPZ4GqYoGd+6ZyYXYY0OZXrNGHQQVj2iVs1ulsvQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=KDqCT2+0; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="KDqCT2+0" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 334F71F000E9; Tue, 21 Jul 2026 19:22:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1784661728; bh=rF4K00/zXX2H13lMISOnAklRF5yoF0uSp4jkK3QEqgg=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=KDqCT2+0z5ckfZXF/jgkeQG1MM+q4/CC7eDlZrxCzvc6W3BQCUBGkmAeGfdkKDzLL PoFW6hYm8Caa0NWTPBS3e6RiWG9CoF4wbC3rbyVuqX9Oj3FJ4p+ptgyzoTOyOVhASV EqwnjdZ1z1D55CHjxmSVXdTd3gNpBedu4ArTAX/s= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Konrad Dybcio , Kuldeep Singh , Harshal Dev , Bjorn Andersson , Sasha Levin Subject: [PATCH 6.12 0139/1276] arm64: dts: qcom: sc7180: Add power-domain and iface clk for ice node Date: Tue, 21 Jul 2026 17:09:42 +0200 Message-ID: <20260721152449.211750681@linuxfoundation.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260721152446.065700225@linuxfoundation.org> References: <20260721152446.065700225@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.12-stable review patch. If anyone has any objections, please let me know. ------------------ From: Harshal Dev [ Upstream commit 7cd7271ac525e4eadd22734f418219f247638f43 ] Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if the UFS_PHY_GDSC power domain is enabled. Specify both the UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for sc7180. Fixes: 858536d9dc946 ("arm64: dts: qcom: sc7180: Add UFS nodes") Reviewed-by: Konrad Dybcio Reviewed-by: Kuldeep Singh Signed-off-by: Harshal Dev Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-6-5ccf5d7e2846@oss.qualcomm.com Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 6ae5ca00c7187a..e52d938df1bece 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1601,7 +1601,11 @@ ice: crypto@1d90000 { compatible = "qcom,sc7180-inline-crypto-engine", "qcom,inline-crypto-engine"; reg = <0 0x01d90000 0 0x8000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>; + clock-names = "core", + "iface"; + power-domains = <&gcc UFS_PHY_GDSC>; }; ipa: ipa@1e40000 { -- 2.53.0