From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A41A3770B; Tue, 21 Jul 2026 20:37:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784666234; cv=none; b=IK6TzB/2dyRjPFltyxnidakDRgxKL0ETlT6zYeT9QeSxzAy3eUZLM1XzhG7IG1bx3Sa0yk/6r5+5GaeI5z2FR8v6kQVkOMoJdisHvy4L8O2gSR+u9BmqStFQof0CvT0ZdwLN3oYVd+45kcRoMX5rSDoA1ReHlkm5blUBqpKxgik= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784666234; c=relaxed/simple; bh=CBsWxKpfIouFUGhwy2u7b8PFSj6nTwQ99FLdAY9iw08=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dWeAZe/vg2KGzw3yZMTW8uh8r03LHC8IbKYTwS/ogxXIaFWYu7np0q071Fu1uXN0X2u7sPkpYDV5p2QvzAMOUI280DUGCH6T8vynY8TgGNmlG8GQGjMl5IhvTyzbhwtV89cS7P6VS0MZ3B3XFuc1RxSvTk5C4PqrqgiXvXP6uE8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=RmS/AlhL; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="RmS/AlhL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 72A861F000E9; Tue, 21 Jul 2026 20:37:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1784666232; bh=50i7XHyi5PnnzdJgSMUf/BE1oqdqSA4gPzs/ODmq4zI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=RmS/AlhLinNX/oX34LmMyX+wLZqApKW+g76vi4GQfRrGg54hG1O+CCSIgZTWpCWAv i6UVz00aHv+tOliJeEgdhLHVYhDVOZEWsurD3mD3cRIcsCqCG3r64FAn47gOPVePvn djAgzigZKLqzmweZc7+jIn+NaZkbMnVc65/qG4jE= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Leo Yan , James Clark , Suzuki K Poulose , Sasha Levin Subject: [PATCH 6.6 0606/1266] coresight: etm4x: Correct TRCVMIDCCTLR1 save and restore Date: Tue, 21 Jul 2026 17:17:23 +0200 Message-ID: <20260721152455.424458464@linuxfoundation.org> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260721152441.786066624@linuxfoundation.org> References: <20260721152441.786066624@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.6-stable review patch. If anyone has any objections, please let me know. ------------------ From: Leo Yan [ Upstream commit 0ec0a8785d21f63db520bd9d2a67c55e855d36a8 ] It is a typo to use trcvmidcctlr0 to save and restore TRCVMIDCCTLR1. Use trcvmidcctlr1 instead. Fixes: f5bd523690d2 ("coresight: etm4x: Convert all register accesses") Signed-off-by: Leo Yan Reviewed-by: James Clark Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/20260408-arm_cs_fix_trcvmidcctlr1_typo-v1-1-6a5695363b46@arm.com Signed-off-by: Sasha Levin --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index c5928f63475a06..331df260d07451 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1837,7 +1837,7 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0); if (drvdata->numvmidc > 4) - state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1); + state->trcvmidcctlr1 = etm4x_read32(csa, TRCVMIDCCTLR1); state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR); @@ -1963,7 +1963,7 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0); if (drvdata->numvmidc > 4) - etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1); + etm4x_relaxed_write32(csa, state->trcvmidcctlr1, TRCVMIDCCTLR1); etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET); -- 2.53.0