From: Richard Cheng <icheng@nvidia.com>
To: tony.luck@intel.com, reinette.chatre@intel.com, x86@kernel.org
Cc: Dave.Martin@arm.com, james.morse@arm.com, babu.moger@amd.com,
shuah@kernel.org, linux-kernel@vger.kernel.org,
linux-kselftest@vger.kernel.org, newtonl@nvidia.com,
kristinc@nvidia.com, kobak@nvidia.com, kaihengf@nvidia.com,
fenghuay@nvidia.com, ltrager@nvidia.com,
"Richard Cheng" <icheng@nvidia.com>,
"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Subject: [PATCH v4 3/3] selftests/resctrl: Recognise aarch64 as a vendor for L3_NONCONT_CAT
Date: Wed, 22 Jul 2026 11:59:43 +0800 [thread overview]
Message-ID: <20260722035943.32337-4-icheng@nvidia.com> (raw)
In-Reply-To: <20260722035943.32337-1-icheng@nvidia.com>
aarch64 has no vendor_id in /proc/cpuinfo, so detect_vendor() returns 0
and arch_supports_noncont_cat() falls through to "return false".
L3_NONCONT_CAT therefore spuriously fails on every ARM MPAM platform.
Define ARCH_ARM, short-circuit detect_vendor() to it on aarch64, and
add it to the AMD/Hygon always-supports early-out in
arch_supports_noncont_cat().
aarch64 has many implementers (ARM 0x41, NVIDIA 0x43, etc.), but MPAM
mandates non-contiguous CPBM uniformly, so per-implementer handling is
not needed here.
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Signed-off-by: Richard Cheng <icheng@nvidia.com>
---
tools/testing/selftests/resctrl/cat_test.c | 9 ++++++--
tools/testing/selftests/resctrl/resctrl.h | 1 +
.../testing/selftests/resctrl/resctrl_tests.c | 21 +++++++++++++++++++
3 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/tools/testing/selftests/resctrl/cat_test.c b/tools/testing/selftests/resctrl/cat_test.c
index 692860c7ce59..55aca0af02c4 100644
--- a/tools/testing/selftests/resctrl/cat_test.c
+++ b/tools/testing/selftests/resctrl/cat_test.c
@@ -271,8 +271,13 @@ static bool arch_supports_noncont_cat(const struct resctrl_test *test)
{
unsigned int vendor_id = get_vendor();
- /* AMD and Hygon always support non-contiguous CBM. */
- if (vendor_id == ARCH_AMD || vendor_id == ARCH_HYGON)
+ /*
+ * AMD and Hygon always support non-contiguous CBM. ARM/MPAM defines
+ * MPAMCFG_CPBM as a bitmap with no contiguity constraint per ARM
+ * DDI 0598.
+ */
+ if (vendor_id == ARCH_AMD || vendor_id == ARCH_HYGON ||
+ vendor_id == ARCH_ARM)
return true;
#if defined(__i386__) || defined(__x86_64__) /* arch */
diff --git a/tools/testing/selftests/resctrl/resctrl.h b/tools/testing/selftests/resctrl/resctrl.h
index ad1c17c0b0bf..5c752fc5d470 100644
--- a/tools/testing/selftests/resctrl/resctrl.h
+++ b/tools/testing/selftests/resctrl/resctrl.h
@@ -40,6 +40,7 @@
#define ARCH_INTEL BIT(0)
#define ARCH_AMD BIT(1)
#define ARCH_HYGON BIT(2)
+#define ARCH_ARM BIT(3)
#define END_OF_TESTS 1
diff --git a/tools/testing/selftests/resctrl/resctrl_tests.c b/tools/testing/selftests/resctrl/resctrl_tests.c
index 593f0ca5251b..57f9f9c0992b 100644
--- a/tools/testing/selftests/resctrl/resctrl_tests.c
+++ b/tools/testing/selftests/resctrl/resctrl_tests.c
@@ -24,6 +24,15 @@ static struct resctrl_test *resctrl_tests[] = {
&l2_noncont_cat_test,
};
+static bool detect_aarch64(void)
+{
+#if defined(__aarch64__)
+ return true;
+#else
+ return false;
+#endif
+}
+
static unsigned int detect_vendor(void)
{
static unsigned int vendor_id;
@@ -35,6 +44,18 @@ static unsigned int detect_vendor(void)
if (initialized)
return vendor_id;
+ if (detect_aarch64()) {
+ /*
+ * aarch64 has no userspace vendor_id in /proc/cpuinfo.
+ * MPAM-capable ARM implementations follow ARM DDI 0598;
+ * treat all aarch64 builds as a single vendor for the
+ * purposes of resctrl selftests.
+ */
+ vendor_id = ARCH_ARM;
+ initialized = true;
+ return vendor_id;
+ }
+
inf = fopen("/proc/cpuinfo", "r");
if (!inf) {
vendor_id = 0;
--
2.43.0
prev parent reply other threads:[~2026-07-22 4:00 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-22 3:59 [PATCH v4 0/3] selftests/resctrl: Fix resctrl selftests issues on aarch64 Richard Cheng
2026-07-22 3:59 ` [PATCH v4 1/3] selftests/resctrl: Skip L3_CAT when no exclusive cache portion exists Richard Cheng
2026-07-22 3:59 ` [PATCH v4 2/3] selftests/resctrl: Implement cl_flush() and sb() for aarch64 Richard Cheng
2026-07-22 3:59 ` Richard Cheng [this message]
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