From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from verein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A99CC34EEF7 for ; Wed, 22 Jul 2026 09:04:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.95.11.211 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784711075; cv=none; b=kaIvFCvkRtGHOj6hGKXbf60IytLWWuQycOrRulG6cIYe1Q9GwL5sQ+k/2urG/Q+b5/Dik/M4u1F1im+pgMaU+sMq+LKiPzQZdaKjYqdkFNprsoM51jBuksCB6mh0m2drJiKUuOx+Hyx/Hnrp3DOLkLKhmz/xquUPP4vnTLbpFR4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784711075; c=relaxed/simple; bh=I0ajmfxwTwn61TyeH5ATuH21kV20t8dMbQahwLOssfk=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=Zr25L6aV7Xbdn++sQuex4lMnvqFWWdL2ypm7krowiaoOoqbfDSx24whBa9JqhWmcavFJP6ugH8DnC/+8x89sMmPQ+aVstPBX45Alt1R6eq+i+3T/bZHhz9vYqfqDIcblskDroraRtGZhCbdFP8pYabQcOBWMSeIOaIMvq9H1q/4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lst.de; spf=pass smtp.mailfrom=lst.de; arc=none smtp.client-ip=213.95.11.211 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lst.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=lst.de Received: by verein.lst.de (Postfix, from userid 2407) id 7355568D37; Wed, 22 Jul 2026 11:04:29 +0200 (CEST) Date: Wed, 22 Jul 2026 11:04:28 +0200 From: Christoph Hellwig To: changfengnan Cc: Keith Busch , Christoph Hellwig , axboe , sagi , "andriy.shevchenko" , "gang.cao" , "jun.i.jin" , "jun1.zeng" , "liang.a.fang" , linux-kernel , linux-nvme , tglx , "yong.hu" , guzebing@bytedance.com Subject: Re: [PATCH v1 1/1] nvme-pci: adaptive interrupt coalescing Message-ID: <20260722090428.GA30753@lst.de> References: <20260715075703.15578-1-jun1.zeng@intel.com> <20260715075703.15578-2-jun1.zeng@intel.com> <20260720150539.GB17986@lst.de> <20260721083739.69676-1-changfengnan@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.5.17 (2007-11-01) On Wed, Jul 22, 2026 at 10:22:11AM +0800, changfengnan wrote: > > > From: "Keith Busch" > > Date:  Tue, Jul 21, 2026, 23:11 > > Subject:  Re: [PATCH v1 1/1] nvme-pci: adaptive interrupt coalescing > > To: "Fengnan Chang" > > Cc: , , , , , , , , , , , , > > On Tue, Jul 21, 2026 at 04:37:39PM +0800, Fengnan Chang wrote: > > > @@ -1618,6 +1748,8 @@ static inline bool nvme_poll_cq(struct nvme_queue *nvmeq, > > >                   * the cqe requires a full read memory barrier > > >                   */ > > >                  dma_rmb(); > > > +                if (sq_head) > > > +                        *sq_head = le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].sq_head); > >  > > This is the wrong criteria to determine the outstanding depth. The spec > > allows the controller to move this forward after it has read an entry. > > The commands may still be in progress, so the depth of future > > completions to expect can't depend on this value. > >  > > But in general, I agree with the spirit of where this is going. > > Thanks for your feedback.  I’d like to hear more opinions from others.  > If this is the right direction, I’ll continue to improve this patch. > > Hi Jens, Christoph, Sagi:  > what do you think? Yes, this is a useful idea, please continue with it if you can.