[RFC PATCH 2/2] drm/xe: Add DRM_XE_DEBUG_FLUSH_WA to force the CPU flush workaround on

[Matthew Brost <matthew.brost@intel.com>]

Add a DRM_XE_DEBUG_FLUSH_WA debug Kconfig option, depending on
DRM_XE_DEBUG, that unconditionally forces xe->info.needs_flush_wa on
regardless of the detected host CPU. This lets driver developers
exercise the LNL_FLUSH_WORKQUEUE()/xe_guc_ct_flush_g2h_worker() code
paths (including the new best-effort scheduling-delay detection and
warnings) on CPUs that aren't otherwise affected.

Cc: Tales A. Mendonça <talesam@gmail.com>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Assisted-by: GitHub Copilot:claude-sonnet-5
---
 drivers/gpu/drm/xe/Kconfig.debug     | 16 ++++++++++++++++
 drivers/gpu/drm/xe/xe_device_types.h |  3 ++-
 drivers/gpu/drm/xe/xe_pci.c          |  3 ++-
 3 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/Kconfig.debug b/drivers/gpu/drm/xe/Kconfig.debug
index 01227c77f6d7..f0332e061453 100644
--- a/drivers/gpu/drm/xe/Kconfig.debug
+++ b/drivers/gpu/drm/xe/Kconfig.debug
@@ -112,3 +112,19 @@ config DRM_XE_USERPTR_INVAL_INJECT
 
 	 Recommended for driver developers only.
 	 If in doubt, say "N".
+
+config DRM_XE_DEBUG_FLUSH_WA
+	bool "Force enable the workqueue/work flush scheduling latency workaround"
+	depends on DRM_XE_DEBUG
+	default n
+	help
+	  Unconditionally enable the workaround for the workqueue/work
+	  scheduling latency issue seen on some Intel hybrid
+	  (Performance + Efficiency core) client CPUs (see
+	  xe_device_has_flush_wa()), regardless of the host CPU actually
+	  running the driver. Useful for exercising/debugging the
+	  workaround's code paths on CPUs that aren't otherwise affected.
+
+	  Recommended for driver developers only.
+
+	  If in doubt, say "N".
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 853a39579686..2dfdce200be7 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -229,7 +229,8 @@ struct xe_device {
 		 * execution by more than a second. This is a property of the
 		 * host CPU (hybrid Performance + Efficiency core designs up
 		 * to and including Arrow Lake), not of the GPU platform, so
-		 * it must not be inferred from xe->info.platform.
+		 * it must not be inferred from xe->info.platform. Forced on
+		 * unconditionally when CONFIG_DRM_XE_DEBUG_FLUSH_WA=y.
 		 */
 		u8 needs_flush_wa:1;
 	} info;
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 4d6e1b544188..ff04e37dbea9 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -827,7 +827,8 @@ static int xe_info_init_early(struct xe_device *xe,
 	 * paired with a discrete GPU, so this cannot be derived from
 	 * desc/platform.
 	 */
-	xe->info.needs_flush_wa = xe_cpu_has_hybrid_flush_wa();
+	xe->info.needs_flush_wa = IS_ENABLED(CONFIG_DRM_XE_DEBUG_FLUSH_WA) ||
+		xe_cpu_has_hybrid_flush_wa();
 
 	xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) &&
 				 xe_modparam.probe_display &&
-- 
2.34.1