Re: [PATCH] pinctrl: sunxi: A523: fix voltage withstand encoding

[Andre Przywara <andre.przywara@arm.com>]

On Wed, 22 Jul 2026 19:23:56 +0200
Juan Manuel López Carrillo <juanmanuellopezcarrillo@gmail.com> wrote:

Hi Juan,

> Hi Andre,
> 
> Tested-by: Juan Manuel Lopez Carrillo <juanmanuellopezcarrillo@gmail.com>
> 
> I hit this exact bug on the Orange Pi 4A (T527) from the Ethernet side, so this
> confirms the "reportedly Ethernet" with a concrete hardware data point.

Thanks, this odd patch of yours (poking POW_MOD_SEL in
pinctrl-sun55i-a523.c) actually made me connect the dots: I looked at
that patch last week, more randomly and out of curiosity, but dismissed
it initially. Then Sashiko commented on my "overvolting" patch pointing
out it changes the "withstand" programming, which reminded me of that
"reversed bits" situation, and I could confirm this with the manual and
an experiment.

> Without the fix, GMAC1 (RGMII, YT8531 PHY) is RX-dead: the link comes up at
> 1Gbps but rx_packets stays 0, so DHCP never completes and the board is
> unreachable. The PJ bank rail is 1.8V, but POW_MOD_SEL was left in 3.3V mode, so
> the RGMII input thresholds were wrong and the MAC never saw RXC/RXD.
> 
> With your patch applied, RX comes back: the board gets a DHCP lease, and a 500 MB
> transfer lands with ~365k rx_packets and rx_crc_errors = 0. So the CTL_INV
> variant fixes it the right way, at the driver level.

Great to hear that, and thanks for testing! There is more to enabling
Ethernet on the box, though, right? The EMAC25M pin needs to be
configured correctly - not even sure that works cleanly with mainline?
And what are the delay values that work for you?
The BSP install on my box is dead, so I cannot poke around there easily.
 
> For transparency on what I actually tested: I applied it on top of current
> mainline (torvalds 248951ddc14d, v7.2-rc4 + a few). It didn't apply cleanly there

Ah yeah, sorry, just saw that I made it in top of my WIP A733 pinctrl
series. I should apply rather cleanly to v7.2-rc1, no?

> — it looks based on a newer pinctrl-sunxi tree — so I rebased one hunk (the
> BIAS_VOLTAGE_PIO_POW_MODE_CTL_INV case in sunxi_pinctrl_set_io_bias_cfg()) onto
> that tree; the change itself is unchanged.
> 
> FWIW I'd independently reverse-engineered the same inverted encoding (bit=1 ->
> 3.3V mode on the A523, vs earlier SoCs; the BSP calls it "power_mode_reverse"),
> so this matches what I saw on hardware, and I'm glad it's handled generically now
> instead of my board-specific DT hack.
> 
> One note from poking at this, in case it's useful for edge cases: on this board a
> few banks behave specially — PF is the SD UHS 1.8/3.3V switch (best left alone),
> and PB/PH take their voltage from VCCIO rather than a per-bank bit. Happy to test

But that is true for all Allwinner SoCs, basically: some ports are
powered by the same VCCIO power pin (typically at 3.3V), and there is
no per-bank supply pin. Look at the data sheet (not user manual), that
mentions that. Also we have a comment to that effect in the DT.

Cheers,
Andre

> those paths on hardware if useful.
> 
> Thanks,
> Juan Manuel
>