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Thu, 23 Jul 2026 02:23:06 +0000 From: Jamin Lin To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Kane Chen , Andrew Jeffery , Joel Stanley , Pierrick Bouvier , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: Jamin Lin , Troy Lee , =?iso-8859-1?Q?Philippe_Mathieu-Daud=E9?= Subject: [PATCH v6 04/11] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap Thread-Topic: [PATCH v6 04/11] hw/arm/ast27x0: Add DRAM alias for SSP SDRAM remap Thread-Index: AQHdGkoyNVbtC9f3JkWfD1cwcvqKnw== Date: Thu, 23 Jul 2026 02:23:06 +0000 Message-ID: <20260723022300.4174471-5-jamin_lin@aspeedtech.com> References: <20260723022300.4174471-1-jamin_lin@aspeedtech.com> In-Reply-To: <20260723022300.4174471-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: TYZPR06MB4980:EE_|KL1PR06MB7034:EE_ x-ms-office365-filtering-correlation-id: 67f215fa-5335-4f5d-cbe4-08dee86154a6 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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envelope-from=jamin_lin@aspeedtech.com; helo=OS8PR02CU002.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This commit adds two MemoryRegion aliases to support PSP access to=0A= SSP SDRAM through shared memory remapping.=0A= =0A= The SSP exposes two DRAM aliases:=0A= - remap1 maps PSP DRAM at 0x400000000 to SSP SDRAM offset 0x5880000=0A= - remap2 maps PSP DRAM at 0x42C000000 to SSP SDRAM offset 0x0=0A= =0A= These mappings follow the default SCU register configuration used by=0A= the ASPEED SDK firmware, which defines the memory window mapping=0A= between PSP and the SSP.=0A= =0A= The alias MemoryRegions belong to the SSP coprocessor state itself=0A= (Aspeed27x0CoprocessorState), since that is what they represent; the=0A= SCU only holds pointers to them (ssp_remap[0]/ssp_remap[1]) so its=0A= control registers can reposition/resize the aliases at runtime. These=0A= can't be QOM link properties since the SCU is already realized by the=0A= time the SSP sets them, so the pointers are written in directly.=0A= =0A= The SSP cpu_index is only known once the SSP's armv7m core is=0A= realized, so it is written directly into the shared SCU at that=0A= point. Its "not wired up" default of -1 is now set explicitly in the=0A= SCU's own realize(), since nothing else sets it via a QOM property=0A= anymore.=0A= =0A= Signed-off-by: Jamin Lin =0A= Tested-by: Philippe Mathieu-Daud=E9 =0A= ---=0A= include/hw/arm/aspeed_coprocessor.h | 2 ++=0A= include/hw/misc/aspeed_scu.h | 3 +++=0A= hw/arm/aspeed_ast27x0-fc.c | 2 ++=0A= hw/arm/aspeed_ast27x0-ssp.c | 38 +++++++++++++++++++++++++++++=0A= hw/misc/aspeed_scu.c | 3 +++=0A= 5 files changed, 48 insertions(+)=0A= =0A= diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_co= processor.h=0A= index 23c3b97f06..d9d0ae7b6d 100644=0A= --- a/include/hw/arm/aspeed_coprocessor.h=0A= +++ b/include/hw/arm/aspeed_coprocessor.h=0A= @@ -52,6 +52,8 @@ struct Aspeed27x0CoprocessorState {=0A= MemoryRegion scu_alias;=0A= MemoryRegion scuio_alias;=0A= MemoryRegion fmc_alias;=0A= + MemoryRegion dram_remap[2];=0A= + MemoryRegion *dram;=0A= Aspeed2700SCUState *scu;=0A= AspeedSCUState *scuio;=0A= AspeedSMCState *fmc;=0A= diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h=0A= index 904549465f..01e8854104 100644=0A= --- a/include/hw/misc/aspeed_scu.h=0A= +++ b/include/hw/misc/aspeed_scu.h=0A= @@ -44,6 +44,9 @@ struct AspeedSCUState {=0A= =0A= struct Aspeed2700SCUState {=0A= AspeedSCUState parent_obj;=0A= +=0A= + MemoryRegion *ssp_remap[2];=0A= + int ssp_cpuid;=0A= };=0A= =0A= #define AST2400_A1_SILICON_REV 0x02010303U=0A= diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c=0A= index 058cea42ed..af700e748f 100644=0A= --- a/hw/arm/aspeed_ast27x0-fc.c=0A= +++ b/hw/arm/aspeed_ast27x0-fc.c=0A= @@ -155,6 +155,8 @@ static bool ast2700fc_ssp_init(Ast2700FCState *s, Aspee= dSoCState *psp,=0A= &error_abort);=0A= object_property_set_link(OBJECT(&s->ssp), "sram",=0A= OBJECT(&psp->sram), &error_abort);=0A= + object_property_set_link(OBJECT(&s->ssp), "dram",=0A= + OBJECT(psp->dram_mr), &error_abort);=0A= object_property_set_link(OBJECT(&s->ssp), "scu",=0A= OBJECT(&s->ca35.scu), &error_abort);=0A= object_property_set_link(OBJECT(&s->ssp), "scuio",=0A= diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c=0A= index 9c984d23cd..2b0cf5041f 100644=0A= --- a/hw/arm/aspeed_ast27x0-ssp.c=0A= +++ b/hw/arm/aspeed_ast27x0-ssp.c=0A= @@ -184,6 +184,12 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState = *dev_soc, Error **errp)=0A= return;=0A= }=0A= =0A= + if (!a->dram) {=0A= + error_setg(errp, TYPE_ASPEED27X0SSP_COPROCESSOR=0A= + ": 'dram' link is not set");=0A= + return;=0A= + }=0A= +=0A= /* AST27X0 SSP Core */=0A= armv7m =3D DEVICE(&a->armv7m);=0A= qdev_prop_set_uint32(armv7m, "num-irq", 256);=0A= @@ -201,6 +207,12 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState = *dev_soc, Error **errp)=0A= &error_abort);=0A= sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);=0A= =0A= + /*=0A= + * cpu_index is only known once the armv7m core above is realized;=0A= + * write it directly into the shared SCU.=0A= + */=0A= + a->scu->ssp_cpuid =3D CPU(a->armv7m.cpu)->cpu_index;=0A= +=0A= /* SDRAM */=0A= sdram_name =3D g_strdup_printf("aspeed.sdram.%d",=0A= CPU(a->armv7m.cpu)->cpu_index);=0A= @@ -232,6 +244,30 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState = *dev_soc, Error **errp)=0A= memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCUIO],= =0A= &a->scuio_alias);=0A= =0A= + /*=0A= + * DRAM remap aliases used by PSP to access SSP SDRAM:=0A= + * - remap[0] maps PSP DRAM at 0x400000000 (size: 0x1A77E000) to=0A= + * SSP SDRAM offset 0x5880000=0A= + * - remap[1] maps PSP DRAM at 0x42C000000 (size: 0x05880000) to=0A= + * SSP SDRAM offset 0x0=0A= + */=0A= + memory_region_init_alias(&a->dram_remap[0], OBJECT(a), "ssp.dram.remap= 1",=0A= + a->dram, 0, 0x1a77e000);=0A= + memory_region_init_alias(&a->dram_remap[1], OBJECT(a), "ssp.dram.remap= 2",=0A= + a->dram, 0x2c000000, 0x05880000);=0A= + memory_region_add_subregion(&s->sdram, 0, &a->dram_remap[1]);=0A= + memory_region_add_subregion(&s->sdram,=0A= + memory_region_size(&a->dram_remap[1]),=0A= + &a->dram_remap[0]);=0A= +=0A= + /*=0A= + * The SCU is already realized at this point (it belongs to the PSP,= =0A= + * which is realized before the SSP), so the remaps are linked in=0A= + * directly instead of via QOM properties.=0A= + */=0A= + a->scu->ssp_remap[0] =3D &a->dram_remap[0];=0A= + a->scu->ssp_remap[1] =3D &a->dram_remap[1];=0A= +=0A= /* INTC */=0A= if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {=0A= return;=0A= @@ -317,6 +353,8 @@ static const Property aspeed_27x0_coprocessor_propertie= s[] =3D {=0A= TYPE_ASPEED_SCU, AspeedSCUState *),=0A= DEFINE_PROP_LINK("fmc", Aspeed27x0CoprocessorState, fmc, TYPE_ASPEED_S= MC,=0A= AspeedSMCState *),=0A= + DEFINE_PROP_LINK("dram", Aspeed27x0CoprocessorState, dram,=0A= + TYPE_MEMORY_REGION, MemoryRegion *),=0A= };=0A= =0A= static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass,=0A= diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c=0A= index ca93c3699d..4025ea3205 100644=0A= --- a/hw/misc/aspeed_scu.c=0A= +++ b/hw/misc/aspeed_scu.c=0A= @@ -932,6 +932,9 @@ static void aspeed_ast2700_scu_reset_hold(Object *obj, = ResetType type)=0A= =0A= static void aspeed_2700_scu_realize(DeviceState *dev, Error **errp)=0A= {=0A= + Aspeed2700SCUState *a =3D ASPEED_2700_SCU(dev);=0A= +=0A= + a->ssp_cpuid =3D -1;=0A= aspeed_scu_realize(dev, errp);=0A= }=0A= =0A= -- =0A= 2.43.0=0A=