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Thu, 23 Jul 2026 02:23:07 +0000 From: Jamin Lin To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Kane Chen , Andrew Jeffery , Joel Stanley , Pierrick Bouvier , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: Jamin Lin , Troy Lee , =?iso-8859-1?Q?Philippe_Mathieu-Daud=E9?= Subject: [PATCH v6 05/11] hw/arm/ast27x0: Add DRAM alias for TSP SDRAM remap Thread-Topic: [PATCH v6 05/11] hw/arm/ast27x0: Add DRAM alias for TSP SDRAM remap Thread-Index: AQHdGkoycQkwEXOFZUKo9UL+EZiwQA== Date: Thu, 23 Jul 2026 02:23:07 +0000 Message-ID: <20260723022300.4174471-6-jamin_lin@aspeedtech.com> References: <20260723022300.4174471-1-jamin_lin@aspeedtech.com> In-Reply-To: <20260723022300.4174471-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: TYZPR06MB4980:EE_|KL1PR06MB7034:EE_ x-ms-office365-filtering-correlation-id: ec68df1b-77c1-4dab-3851-08dee861556f x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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envelope-from=jamin_lin@aspeedtech.com; helo=TYPPR03CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This commit adds a MemoryRegion alias to support PSP access to=0A= TSP SDRAM through shared memory remapping.=0A= =0A= The TSP coprocessor exposes one DRAM alias:=0A= - remap maps PSP DRAM at 0x42E000000 to TSP SDRAM offset 0x0=0A= =0A= These mappings follow the default SCU register configuration used by=0A= the ASPEED SDK firmware, which defines the memory window mapping=0A= between PSP and TSP.=0A= =0A= The alias MemoryRegion belongs to the TSP coprocessor state itself=0A= (Aspeed27x0CoprocessorState), mirroring the SSP remap; the SCU only=0A= holds a pointer to it (tsp_remap) so its control registers can=0A= reposition/resize the alias at runtime. This can't be a QOM link=0A= property since the SCU is already realized by the time the TSP sets=0A= it, so the pointer is written in directly.=0A= =0A= The TSP cpu_index is only known once the TSP's armv7m core is=0A= realized, so it is written directly into the shared SCU at that=0A= point. Its "not wired up" default of -1 is now set explicitly in the=0A= SCU's own realize(), since nothing else sets it via a QOM property=0A= anymore.=0A= =0A= Signed-off-by: Jamin Lin =0A= Tested-by: Philippe Mathieu-Daud=E9 =0A= ---=0A= include/hw/misc/aspeed_scu.h | 2 ++=0A= hw/arm/aspeed_ast27x0-fc.c | 2 ++=0A= hw/arm/aspeed_ast27x0-tsp.c | 30 ++++++++++++++++++++++++++++++=0A= hw/misc/aspeed_scu.c | 1 +=0A= 4 files changed, 35 insertions(+)=0A= =0A= diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h=0A= index 01e8854104..aef13e8915 100644=0A= --- a/include/hw/misc/aspeed_scu.h=0A= +++ b/include/hw/misc/aspeed_scu.h=0A= @@ -46,7 +46,9 @@ struct Aspeed2700SCUState {=0A= AspeedSCUState parent_obj;=0A= =0A= MemoryRegion *ssp_remap[2];=0A= + MemoryRegion *tsp_remap;=0A= int ssp_cpuid;=0A= + int tsp_cpuid;=0A= };=0A= =0A= #define AST2400_A1_SILICON_REV 0x02010303U=0A= diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c=0A= index af700e748f..e51d8024eb 100644=0A= --- a/hw/arm/aspeed_ast27x0-fc.c=0A= +++ b/hw/arm/aspeed_ast27x0-fc.c=0A= @@ -191,6 +191,8 @@ static bool ast2700fc_tsp_init(Ast2700FCState *s, Aspee= dSoCState *psp,=0A= &error_abort);=0A= object_property_set_link(OBJECT(&s->tsp), "sram",=0A= OBJECT(&psp->sram), &error_abort);=0A= + object_property_set_link(OBJECT(&s->tsp), "dram",=0A= + OBJECT(psp->dram_mr), &error_abort);=0A= object_property_set_link(OBJECT(&s->tsp), "scu",=0A= OBJECT(&s->ca35.scu), &error_abort);=0A= object_property_set_link(OBJECT(&s->tsp), "scuio",=0A= diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c=0A= index 4212e7bd4c..9a860f6ea3 100644=0A= --- a/hw/arm/aspeed_ast27x0-tsp.c=0A= +++ b/hw/arm/aspeed_ast27x0-tsp.c=0A= @@ -184,6 +184,12 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState = *dev_soc, Error **errp)=0A= return;=0A= }=0A= =0A= + if (!a->dram) {=0A= + error_setg(errp, TYPE_ASPEED27X0TSP_COPROCESSOR=0A= + ": 'dram' link is not set");=0A= + return;=0A= + }=0A= +=0A= /* AST27X0 TSP Core */=0A= armv7m =3D DEVICE(&a->armv7m);=0A= qdev_prop_set_uint32(armv7m, "num-irq", 256);=0A= @@ -201,6 +207,12 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState = *dev_soc, Error **errp)=0A= &error_abort);=0A= sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);=0A= =0A= + /*=0A= + * cpu_index is only known once the armv7m core above is realized;=0A= + * write it directly into the shared SCU.=0A= + */=0A= + a->scu->tsp_cpuid =3D CPU(a->armv7m.cpu)->cpu_index;=0A= +=0A= /* SDRAM */=0A= sdram_name =3D g_strdup_printf("aspeed.sdram.%d",=0A= CPU(a->armv7m.cpu)->cpu_index);=0A= @@ -232,6 +244,22 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState = *dev_soc, Error **errp)=0A= memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCUIO],= =0A= &a->scuio_alias);=0A= =0A= + /*=0A= + * DRAM remap alias used by PSP to access TSP SDRAM:=0A= + * - remap maps PSP DRAM at 0x42E000000 (size: 32MB) to TSP SDRAM=0A= + * offset 0x0=0A= + */=0A= + memory_region_init_alias(&a->dram_remap[0], OBJECT(a), "tsp.dram.remap= ",=0A= + a->dram, 0x2e000000, 32 * MiB);=0A= + memory_region_add_subregion(&s->sdram, 0, &a->dram_remap[0]);=0A= +=0A= + /*=0A= + * The SCU is already realized at this point (it belongs to the PSP,= =0A= + * which is realized before the TSP), so the remap is linked in=0A= + * directly instead of via a QOM property.=0A= + */=0A= + a->scu->tsp_remap =3D &a->dram_remap[0];=0A= +=0A= /* INTC */=0A= if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {=0A= return;=0A= @@ -317,6 +345,8 @@ static const Property aspeed_27x0_coprocessor_propertie= s[] =3D {=0A= TYPE_ASPEED_SCU, AspeedSCUState *),=0A= DEFINE_PROP_LINK("fmc", Aspeed27x0CoprocessorState, fmc, TYPE_ASPEED_S= MC,=0A= AspeedSMCState *),=0A= + DEFINE_PROP_LINK("dram", Aspeed27x0CoprocessorState, dram,=0A= + TYPE_MEMORY_REGION, MemoryRegion *),=0A= };=0A= =0A= static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass,=0A= diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c=0A= index 4025ea3205..5d34dbea5e 100644=0A= --- a/hw/misc/aspeed_scu.c=0A= +++ b/hw/misc/aspeed_scu.c=0A= @@ -935,6 +935,7 @@ static void aspeed_2700_scu_realize(DeviceState *dev, E= rror **errp)=0A= Aspeed2700SCUState *a =3D ASPEED_2700_SCU(dev);=0A= =0A= a->ssp_cpuid =3D -1;=0A= + a->tsp_cpuid =3D -1;=0A= aspeed_scu_realize(dev, errp);=0A= }=0A= =0A= -- =0A= 2.43.0=0A=