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Thu, 23 Jul 2026 02:23:08 +0000 From: Jamin Lin To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Kane Chen , Andrew Jeffery , Joel Stanley , Pierrick Bouvier , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: Jamin Lin , Troy Lee , =?iso-8859-1?Q?Philippe_Mathieu-Daud=E9?= Subject: [PATCH v6 06/11] hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU registers Thread-Topic: [PATCH v6 06/11] hw/misc/aspeed_scu: Implement SSP reset and power-on control via SCU registers Thread-Index: AQHdGkozq6jCVKCLWEWAq82GlUPI7g== Date: Thu, 23 Jul 2026 02:23:08 +0000 Message-ID: <20260723022300.4174471-7-jamin_lin@aspeedtech.com> References: <20260723022300.4174471-1-jamin_lin@aspeedtech.com> In-Reply-To: <20260723022300.4174471-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; 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envelope-from=jamin_lin@aspeedtech.com; helo=OS8PR02CU002.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org This patch implements SSP reset and power control logic in the SCU for AST2= 700.=0A= It introduces support for the following behavior:=0A= =0A= 1. SSP Reset Trigger (via SCU 0x200):=0A= - SSP reset is triggered by writing 1 to bit 30 (RW1S) of SYS_RESET_CTRL= _1.=0A= =0A= 2. SSP Reset State and Source Hold (via SCU 0x120):=0A= - Upon reset, bit 8 (RST_RB) is set to indicate the SSP is in reset.=0A= - Bit 10 (RST_SRC_RB) is set to indicate the reset was triggered by an e= xternal source.=0A= - Bit 1 (RST) is a software-controlled bit used to request holding SSP i= n reset.=0A= - If an external reset source is present and bit 1 is set, bit 9 (RST_HO= LD_RB)=0A= will also be asserted to indicate the SSP is being held in reset.=0A= - If bit 1 is cleared, RST_HOLD_RB will be deasserted accordingly.=0A= =0A= 3. Hold Release and Power-on:=0A= - If RST_HOLD_RB is clear (0), SSP is powered on immediately after reset= is deasserted.=0A= - If RST_HOLD_RB is set (1), the user must write ENABLE (bit 0) to SSP_C= TRL_0 to release=0A= the hold and power on SSP explicitly.=0A= - Writing ENABLE (bit 0) is a one-shot operation and will auto-clear aft= er execution.=0A= =0A= 4. Reset Status Clear (via SCU 0x204):=0A= - The reset status can be cleared by writing 1 to bit 30 (RW1C) of SYS_R= ST_CLR_1,=0A= which will deassert RST_SRC_RB and potentially trigger power-on if no = hold is active.=0A= =0A= 5. SSP Power Control Logic:=0A= - `handle_ssp_tsp_on()` clears RST_SRC_RB and RST_RB (if not held), and = invokes=0A= `arm_set_cpu_on_and_reset(cpuid)` to power on the SSP core (CPUID 4).= =0A= - `handle_ssp_tsp_off()` sets RST_RB and RST_SRC_RB; if RST is active, a= lso asserts=0A= RST_HOLD_RB and invokes `arm_set_cpu_off(cpuid)`.=0A= =0A= 6. Register Initialization and Definitions:=0A= - Adds SCU register definitions for SSP_CTRL_0 (0x120), SYS_RST_CTRL_1 (= 0x200),=0A= and SYS_RST_CLR_1 (0x204).=0A= - Updates the reset values for these registers during SCU initialization= .=0A= =0A= The default values are based on EVB (evaluation board) register dump observ= ations.=0A= This patch enables proper modeling of SSP lifecycle management across reset= ,=0A= hold, and power-on states for the AST2700 SoC.=0A= =0A= Signed-off-by: Jamin Lin =0A= Tested-by: Philippe Mathieu-Daud=E9 =0A= ---=0A= hw/misc/aspeed_scu.c | 109 +++++++++++++++++++++++++++++++++++++++++++=0A= 1 file changed, 109 insertions(+)=0A= =0A= diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c=0A= index 5d34dbea5e..0fdeaf5648 100644=0A= --- a/hw/misc/aspeed_scu.c=0A= +++ b/hw/misc/aspeed_scu.c=0A= @@ -20,6 +20,7 @@=0A= #include "qemu/guest-random.h"=0A= #include "qemu/module.h"=0A= #include "trace.h"=0A= +#include "target/arm/arm-powerctl.h"=0A= =0A= #define TO_REG(offset) ((offset) >> 2)=0A= =0A= @@ -143,6 +144,17 @@=0A= #define AST2700_HW_STRAP1_SEC2 TO_REG(0x28)=0A= #define AST2700_HW_STRAP1_SEC3 TO_REG(0x2C)=0A= =0A= +/* SSP TSP */=0A= +#define AST2700_SCU_SSP_CTRL_0 TO_REG(0x120)=0A= +#define AST2700_SSP_TSP_ENABLE BIT(0)=0A= +#define AST2700_SSP_TSP_RST BIT(1)=0A= +#define AST2700_SSP_TSP_RST_RB BIT(8)=0A= +#define AST2700_SSP_TSP_RST_HOLD_RB BIT(9)=0A= +#define AST2700_SSP_TSP_RST_SRC_RB BIT(10)=0A= +#define AST2700_SCU_SYS_RST_CTRL_1 TO_REG(0x200)=0A= +#define AST2700_SCU_SYS_RST_CLR_1 TO_REG(0x204)=0A= +#define AST2700_SCU_SYS_RST_SSP BIT(30)=0A= +=0A= #define AST2700_SCU_CLK_SEL_1 TO_REG(0x280)=0A= #define AST2700_SCU_HPLL_PARAM TO_REG(0x300)=0A= #define AST2700_SCU_HPLL_EXT_PARAM TO_REG(0x304)=0A= @@ -841,6 +853,35 @@ static void aspeed_2600_scu_class_init(ObjectClass *kl= ass, const void *data)=0A= asc->ops =3D &aspeed_ast2600_scu_ops;=0A= }=0A= =0A= +static void handle_2700_ssp_tsp_on(struct AspeedSCUState *s, int cpuid,=0A= + int reg)=0A= +{=0A= + uint32_t val =3D s->regs[reg];=0A= +=0A= + val &=3D ~AST2700_SSP_TSP_RST_SRC_RB;=0A= + if (!(val & AST2700_SSP_TSP_RST_HOLD_RB)) {=0A= + val &=3D ~AST2700_SSP_TSP_RST_RB;=0A= + arm_set_cpu_on_and_reset(cpuid);=0A= + }=0A= +=0A= + s->regs[reg] =3D val;=0A= +}=0A= +=0A= +static void handle_2700_ssp_tsp_off(struct AspeedSCUState *s, int cpuid,= =0A= + int reg)=0A= +{=0A= + uint32_t val =3D s->regs[reg];=0A= +=0A= + val |=3D AST2700_SSP_TSP_RST_RB;=0A= + val |=3D AST2700_SSP_TSP_RST_SRC_RB;=0A= + if (val & AST2700_SSP_TSP_RST) {=0A= + val |=3D AST2700_SSP_TSP_RST_HOLD_RB;=0A= + }=0A= + arm_set_cpu_off(cpuid);=0A= +=0A= + s->regs[reg] =3D val;=0A= +}=0A= +=0A= static uint64_t aspeed_ast2700_scu_read(void *opaque, hwaddr offset,=0A= unsigned size)=0A= {=0A= @@ -861,10 +902,14 @@ static uint64_t aspeed_ast2700_scu_read(void *opaque,= hwaddr offset,=0A= static void aspeed_ast2700_scu_write(void *opaque, hwaddr offset,=0A= uint64_t data64, unsigned size)=0A= {=0A= + Aspeed2700SCUState *a =3D ASPEED_2700_SCU(opaque);=0A= AspeedSCUState *s =3D ASPEED_SCU(opaque);=0A= int reg =3D TO_REG(offset);=0A= /* Truncate here so bitwise operations below behave as expected */=0A= uint32_t data =3D data64;=0A= + uint32_t active;=0A= + uint32_t oldval;=0A= + int cpuid;=0A= =0A= if (reg >=3D ASPEED_AST2700_SCU_NR_REGS) {=0A= qemu_log_mask(LOG_GUEST_ERROR,=0A= @@ -876,6 +921,63 @@ static void aspeed_ast2700_scu_write(void *opaque, hwa= ddr offset,=0A= trace_aspeed_ast2700_scu_write(offset, size, data);=0A= =0A= switch (reg) {=0A= + case AST2700_SCU_SSP_CTRL_0:=0A= + cpuid =3D a->ssp_cpuid;=0A= + if (cpuid < 0) {=0A= + return;=0A= + }=0A= + oldval =3D s->regs[reg];=0A= + data &=3D 0xff;=0A= + active =3D oldval ^ data;=0A= +=0A= + /*=0A= + * If reset bit is being released (1 -> 0) and no other reset sour= ce=0A= + * is active, clear HOLD_RB and power on the corresponding CPU.=0A= + */=0A= + if ((active & AST2700_SSP_TSP_RST) && !(data & AST2700_SSP_TSP_RST= )) {=0A= + s->regs[reg] &=3D ~AST2700_SSP_TSP_RST_HOLD_RB;=0A= + if ((oldval & AST2700_SSP_TSP_RST_RB) &&=0A= + !(oldval & AST2700_SSP_TSP_RST_SRC_RB)) {=0A= + handle_2700_ssp_tsp_on(s, cpuid, reg);=0A= + }=0A= + }=0A= +=0A= + /*=0A= + * If ENABLE bit is newly set and reset state is ready,=0A= + * clear HOLD_RB and power on the corresponding CPU.=0A= + */=0A= + if ((active & AST2700_SSP_TSP_ENABLE) &&=0A= + (oldval & AST2700_SSP_TSP_RST_RB) &&=0A= + (oldval & AST2700_SSP_TSP_RST_HOLD_RB) &&=0A= + !(oldval & AST2700_SSP_TSP_RST_SRC_RB)) {=0A= + s->regs[reg] &=3D ~AST2700_SSP_TSP_RST_HOLD_RB;=0A= + handle_2700_ssp_tsp_on(s, cpuid, reg);=0A= + }=0A= +=0A= + /* Auto-clear the ENABLE bit (one-shot behavior) */=0A= + data &=3D ~AST2700_SSP_TSP_ENABLE;=0A= + s->regs[reg] =3D (s->regs[reg] & ~0xff) | (data & 0xff);=0A= + return;=0A= + case AST2700_SCU_SYS_RST_CTRL_1:=0A= + if (a->ssp_cpuid < 0) {=0A= + return;=0A= + }=0A= + if (data & AST2700_SCU_SYS_RST_SSP) {=0A= + handle_2700_ssp_tsp_off(s, a->ssp_cpuid, AST2700_SCU_SSP_CTRL_= 0);=0A= + }=0A= + s->regs[reg] |=3D data;=0A= + return;=0A= + case AST2700_SCU_SYS_RST_CLR_1:=0A= + if (a->ssp_cpuid < 0) {=0A= + return;=0A= + }=0A= + oldval =3D s->regs[AST2700_SCU_SYS_RST_CTRL_1];=0A= + active =3D data & oldval;=0A= + if (active & AST2700_SCU_SYS_RST_SSP) {=0A= + handle_2700_ssp_tsp_on(s, a->ssp_cpuid, AST2700_SCU_SSP_CTRL_0= );=0A= + }=0A= + s->regs[AST2700_SCU_SYS_RST_CTRL_1] &=3D ~active;=0A= + return;=0A= default:=0A= qemu_log_mask(LOG_GUEST_ERROR,=0A= "%s: Unhandled write at offset 0x%" HWADDR_PRIx "\n"= ,=0A= @@ -903,6 +1005,8 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700= _SCU_NR_REGS] =3D {=0A= [AST2700_HW_STRAP1_SEC1] =3D 0x000000FF,=0A= [AST2700_HW_STRAP1_SEC2] =3D 0x00000000,=0A= [AST2700_HW_STRAP1_SEC3] =3D 0x1000408F,=0A= + [AST2700_SCU_SSP_CTRL_0] =3D 0x000007FE,=0A= + [AST2700_SCU_SYS_RST_CTRL_1] =3D 0xFFC37FDC,=0A= [AST2700_SCU_HPLL_PARAM] =3D 0x0000009f,=0A= [AST2700_SCU_HPLL_EXT_PARAM] =3D 0x8000004f,=0A= [AST2700_SCU_DPLL_PARAM] =3D 0x0080009f,=0A= @@ -922,12 +1026,17 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST27= 00_SCU_NR_REGS] =3D {=0A= =0A= static void aspeed_ast2700_scu_reset_hold(Object *obj, ResetType type)=0A= {=0A= + Aspeed2700SCUState *a =3D ASPEED_2700_SCU(obj);=0A= AspeedSCUState *s =3D ASPEED_SCU(obj);=0A= AspeedSCUClass *asc =3D ASPEED_SCU_GET_CLASS(obj);=0A= =0A= memcpy(s->regs, asc->resets, asc->nr_regs * 4);=0A= s->regs[AST2700_SILICON_REV] =3D s->silicon_rev;=0A= s->regs[AST2700_HW_STRAP1] =3D s->hw_strap1;=0A= +=0A= + if (a->ssp_cpuid > 0) {=0A= + arm_set_cpu_off(a->ssp_cpuid);=0A= + }=0A= }=0A= =0A= static void aspeed_2700_scu_realize(DeviceState *dev, Error **errp)=0A= -- =0A= 2.43.0=0A=