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Thu, 23 Jul 2026 02:23:11 +0000 From: Jamin Lin To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Kane Chen , Andrew Jeffery , Joel Stanley , Pierrick Bouvier , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: Jamin Lin , Troy Lee , =?iso-8859-1?Q?Philippe_Mathieu-Daud=E9?= Subject: [PATCH v6 08/11] hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap Thread-Topic: [PATCH v6 08/11] hw/misc/aspeed_scu: Add SCU support for SSP SDRAM remap Thread-Index: AQHdGko1EBCRL2OUf0iAkg0VzyKmxg== Date: Thu, 23 Jul 2026 02:23:11 +0000 Message-ID: <20260723022300.4174471-9-jamin_lin@aspeedtech.com> References: <20260723022300.4174471-1-jamin_lin@aspeedtech.com> In-Reply-To: <20260723022300.4174471-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: TYZPR06MB4980:EE_|KL1PR06MB7034:EE_ x-ms-office365-filtering-correlation-id: f3c61512-4770-4e87-7a83-08dee86157b7 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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envelope-from=jamin_lin@aspeedtech.com; helo=OS8PR02CU002.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This commit adds SCU register support for SSP SDRAM remap control and runti= me=0A= activation. It introduces logic for the PSP to dynamically configure the ma= pping=0A= of its own DRAM windows into SSP-visible SDRAM space, enabling shared memor= y=0A= communication via memory region aliases.=0A= =0A= - coprocessor_sdram_remap[0]: maps PSP DRAM offset 0x400000000 (size: 0x1A7= 7E000) to SSP SDRAM=0A= offset 0x5880000=0A= - coprocessor_sdram_remap[1]: maps PSP DRAM offset 0x42C000000 (size: 0x058= 80000) to SSP SDRAM=0A= offset 0x0=0A= =0A= The SCU registers AST2700_SCU_SSP_CTRL_1/2 and=0A= AST2700_SCU_SSP_REMAP_ADDR_{1,2} / REMAP_SIZE_{1,2} allow runtime reconfigu= ration=0A= of alias offset, base, and size.=0A= =0A= |------------------------------------------| |---------------------= -------|=0A= | PSP DRAM | | SSP SDRAM = |=0A= |------------------------------------------| |---------------------= -------|=0A= | 0x4_0000_0000 (SCU_124 << 4) | --> | 0x0000_0000 = |=0A= | remap1 base |---| | | - SCU_150: target a= ddr |=0A= | size: 0x1A77E000 (SCU_14C) | | | | remap2 = |=0A= |------------------------------------------| | | |---------------------= -------|=0A= | | | | | = |=0A= | 0x4_2C00_0000 (SCU_128 << 4) |-----| | 0x5880000 = |=0A= | remap2 base | | | - SCU_148: target a= ddr |=0A= | size: 0x05880000 (SCU_154) | |---> | remap1 = |=0A= |------------------------------------------| |---------------------= -------|=0A= =0A= Signed-off-by: Jamin Lin =0A= Tested-by: Philippe Mathieu-Daud=E9 =0A= ---=0A= hw/misc/aspeed_scu.c | 62 ++++++++++++++++++++++++++++++++++++++++++++=0A= 1 file changed, 62 insertions(+)=0A= =0A= diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c=0A= index fdb1cf59b4..407c1743fc 100644=0A= --- a/hw/misc/aspeed_scu.c=0A= +++ b/hw/misc/aspeed_scu.c=0A= @@ -146,6 +146,14 @@=0A= =0A= /* SSP TSP */=0A= #define AST2700_SCU_SSP_CTRL_0 TO_REG(0x120)=0A= +#define AST2700_SCU_SSP_CTRL_1 TO_REG(0x124)=0A= +#define AST2700_SCU_SSP_CTRL_2 TO_REG(0x128)=0A= +#define AST2700_SCU_SSP_REMAP_ADDR_0 TO_REG(0x140)=0A= +#define AST2700_SCU_SSP_REMAP_SIZE_0 TO_REG(0x144)=0A= +#define AST2700_SCU_SSP_REMAP_ADDR_1 TO_REG(0x148)=0A= +#define AST2700_SCU_SSP_REMAP_SIZE_1 TO_REG(0x14C)=0A= +#define AST2700_SCU_SSP_REMAP_ADDR_2 TO_REG(0x150)=0A= +#define AST2700_SCU_SSP_REMAP_SIZE_2 TO_REG(0x154)=0A= #define AST2700_SCU_TSP_CTRL_0 TO_REG(0x160)=0A= #define AST2700_SSP_TSP_ENABLE BIT(0)=0A= #define AST2700_SSP_TSP_RST BIT(1)=0A= @@ -908,6 +916,7 @@ static void aspeed_ast2700_scu_write(void *opaque, hwad= dr offset,=0A= {=0A= Aspeed2700SCUState *a =3D ASPEED_2700_SCU(opaque);=0A= AspeedSCUState *s =3D ASPEED_SCU(opaque);=0A= + MemoryRegion *mr =3D NULL;=0A= int reg =3D TO_REG(offset);=0A= /* Truncate here so bitwise operations below behave as expected */=0A= uint32_t data =3D data64;=0A= @@ -965,6 +974,43 @@ static void aspeed_ast2700_scu_write(void *opaque, hwa= ddr offset,=0A= data &=3D ~AST2700_SSP_TSP_ENABLE;=0A= s->regs[reg] =3D (s->regs[reg] & ~0xff) | (data & 0xff);=0A= return;=0A= + case AST2700_SCU_SSP_CTRL_1:=0A= + case AST2700_SCU_SSP_CTRL_2:=0A= + mr =3D (reg =3D=3D AST2700_SCU_SSP_CTRL_1) ?=0A= + a->ssp_remap[0] : a->ssp_remap[1];=0A= + if (a->ssp_cpuid < 0 || mr =3D=3D NULL) {=0A= + return;=0A= + }=0A= + data &=3D 0x7fffffff;=0A= + memory_region_transaction_begin();=0A= + memory_region_set_alias_offset(mr,=0A= + ((uint64_t) data << 4) & 0x3fffffff= f);=0A= + memory_region_transaction_commit();=0A= + break;=0A= + case AST2700_SCU_SSP_REMAP_ADDR_1:=0A= + case AST2700_SCU_SSP_REMAP_ADDR_2:=0A= + mr =3D (reg =3D=3D AST2700_SCU_SSP_REMAP_ADDR_1) ?=0A= + a->ssp_remap[0] : a->ssp_remap[1];=0A= + if (a->ssp_cpuid < 0 || mr =3D=3D NULL) {=0A= + return;=0A= + }=0A= + data &=3D 0x3fffffff;=0A= + memory_region_transaction_begin();=0A= + memory_region_set_address(mr, data);=0A= + memory_region_transaction_commit();=0A= + break;=0A= + case AST2700_SCU_SSP_REMAP_SIZE_1:=0A= + case AST2700_SCU_SSP_REMAP_SIZE_2:=0A= + mr =3D (reg =3D=3D AST2700_SCU_SSP_REMAP_SIZE_1) ?=0A= + a->ssp_remap[0] : a->ssp_remap[1];=0A= + if (a->ssp_cpuid < 0 || mr =3D=3D NULL) {=0A= + return;=0A= + }=0A= + data &=3D 0x3fffffff;=0A= + memory_region_transaction_begin();=0A= + memory_region_set_size(mr, data);=0A= + memory_region_transaction_commit();=0A= + break;=0A= case AST2700_SCU_SYS_RST_CTRL_1:=0A= if (a->ssp_cpuid < 0) {=0A= return;=0A= @@ -1035,6 +1081,14 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST27= 00_SCU_NR_REGS] =3D {=0A= [AST2700_HW_STRAP1_SEC2] =3D 0x00000000,=0A= [AST2700_HW_STRAP1_SEC3] =3D 0x1000408F,=0A= [AST2700_SCU_SSP_CTRL_0] =3D 0x000007FE,=0A= + [AST2700_SCU_SSP_CTRL_1] =3D 0x40000000,=0A= + [AST2700_SCU_SSP_CTRL_2] =3D 0x42C00000,=0A= + [AST2700_SCU_SSP_REMAP_ADDR_0] =3D 0x1FFFE000,=0A= + [AST2700_SCU_SSP_REMAP_SIZE_0] =3D 0x00002000,=0A= + [AST2700_SCU_SSP_REMAP_ADDR_1] =3D 0x05880000,=0A= + [AST2700_SCU_SSP_REMAP_SIZE_1] =3D 0x1A77E000,=0A= + [AST2700_SCU_SSP_REMAP_ADDR_2] =3D 0x00000000,=0A= + [AST2700_SCU_SSP_REMAP_SIZE_2] =3D 0x05880000,=0A= [AST2700_SCU_TSP_CTRL_0] =3D 0x000007FE,=0A= [AST2700_SCU_SYS_RST_CTRL_1] =3D 0xFFC37FDC,=0A= [AST2700_SCU_SYS_RST_CTRL_2] =3D 0x00001FFF,=0A= @@ -1067,6 +1121,14 @@ static void aspeed_ast2700_scu_reset_hold(Object *ob= j, ResetType type)=0A= =0A= if (a->ssp_cpuid > 0) {=0A= arm_set_cpu_off(a->ssp_cpuid);=0A= + memory_region_transaction_begin();=0A= + memory_region_set_address(a->ssp_remap[0], 0x5880000);=0A= + memory_region_set_alias_offset(a->ssp_remap[0], 0);=0A= + memory_region_set_size(a->ssp_remap[0], 0x1a77e000);=0A= + memory_region_set_address(a->ssp_remap[1], 0);=0A= + memory_region_set_alias_offset(a->ssp_remap[1], 0x2c000000);=0A= + memory_region_set_size(a->ssp_remap[1], 0x5880000);=0A= + memory_region_transaction_commit();=0A= }=0A= =0A= if (a->tsp_cpuid > 0) {=0A= -- =0A= 2.43.0=0A=