From: sashiko-bot@kernel.org
To: "Santhosh Kumar K" <s-k6@ti.com>
Cc: devicetree@vger.kernel.org, "Michael Walle" <mwalle@kernel.org>,
"Takahiro Kuwano" <takahiro.kuwano@infineon.com>,
"Pratyush Yadav" <pratyush@kernel.org>,
"Vignesh Raghavendra" <vigneshr@ti.com>,
"Richard Weinberger" <richard@nod.at>,
robh@kernel.org, conor+dt@kernel.org,
"Miquel Raynal" <miquel.raynal@bootlin.com>
Subject: Re: [PATCH v6 05/17] spi: spi-mem: add execute_tuning callback and spi_mem_execute_tuning()
Date: Thu, 23 Jul 2026 11:30:42 +0000 [thread overview]
Message-ID: <20260723113043.CC2BD1F00A3E@smtp.kernel.org> (raw)
In-Reply-To: <20260723110219.3180747-6-s-k6@ti.com>
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] spi_mem_execute_tuning() directly invokes the controller callback without acquiring the SPI bus locks or ensuring the controller is powered on.
- [High] spi_mem_execute_tuning() does not check if the SPI device is using a GPIO chip select before invoking the hardware tuning callback.
--
--- Patch [5]: [PATCH v6 05/17] spi: spi-mem: add execute_tuning callback and spi_mem_execute_tuning() ---
commit 74cda1abf92afd30bb8cd6cbe4cb6c5ffa5027f5
Author: Santhosh Kumar K <s-k6@ti.com>
spi: spi-mem: add execute_tuning callback and spi_mem_execute_tuning()
This commit adds an execute_tuning callback to struct spi_controller_mem_ops.
It also introduces the spi_mem_execute_tuning() wrapper function to check
callback availability and invoke it.
> diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
> index e20eca1b82457..ae9e2d7ac6f3c 100644
> --- a/drivers/spi/spi-mem.c
> +++ b/drivers/spi/spi-mem.c
[ ... ]
> @@ -660,6 +660,37 @@ u64 spi_mem_calc_op_duration(struct spi_mem *mem, struct spi_mem_op *op)
> }
> EXPORT_SYMBOL_GPL(spi_mem_calc_op_duration);
>
> +/**
> + * spi_mem_execute_tuning() - Execute controller tuning procedure
> + * @mem: the SPI memory device
> + * @read_op: read operation template (mandatory)
> + * @write_op: write operation template (optional, may be NULL)
> + *
> + * Requests the controller to perform tuning for high-speed operation
> + * using the provided op templates. On success the controller callback
> + * sets @read_op->max_freq (and @write_op->max_freq when non-NULL) to
> + * the validated clock rate.
> + *
> + * Return: 0 on success, -EINVAL if @mem or @read_op is NULL,
> + * -EOPNOTSUPP if the controller doesn't support tuning,
> + * or a negative error code on failure.
> + */
> +int spi_mem_execute_tuning(struct spi_mem *mem, struct spi_mem_op *read_op,
> + struct spi_mem_op *write_op)
> +{
> + struct spi_controller *ctlr;
> +
> + if (!mem || !read_op)
> + return -EINVAL;
> +
> + ctlr = mem->spi->controller;
[Severity: High]
Does this code execute hardware tuning operations without acquiring the SPI
bus locks or ensuring the controller is powered on?
Other standard SPI memory operations use spi_mem_access_start() and
spi_mem_access_end() to take the runtime PM reference and provide mutual
exclusion against other ongoing SPI transfers. Since those functions are
internal, external callers cannot acquire these necessary protections
themselves.
Could this lead to hardware lockups or data corruption on the SPI bus?
> + if (!ctlr->mem_ops || !ctlr->mem_ops->execute_tuning)
> + return -EOPNOTSUPP;
> +
> + return ctlr->mem_ops->execute_tuning(mem, read_op, write_op);
[Severity: High]
Should this check if the SPI device is using a GPIO chip select before
delegating to the controller's hardware tuning callback?
Standard SPI memory operations (like spi_mem_exec_op) explicitly check
!spi_get_csgpiod(mem->spi, 0) before delegating to ctlr->mem_ops, because
hardware-level memory controllers operate the native chip select.
If a device is configured with a GPIO chip select, the hardware engine will
toggle the native CS (which might be disconnected or connected to a different
device) instead of the GPIO CS. Does this need a check similar to other
spi_mem operations?
> +}
> +EXPORT_SYMBOL_GPL(spi_mem_execute_tuning);
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260723110219.3180747-1-s-k6@ti.com?part=5
next prev parent reply other threads:[~2026-07-23 11:30 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-23 11:02 [PATCH v6 00/17] spi: cadence-quadspi: add PHY tuning support Santhosh Kumar K
2026-07-23 11:02 ` Santhosh Kumar K
2026-07-23 11:02 ` [PATCH v6 01/17] spi: dt-bindings: add spi-max-post-config-frequency-hz property Santhosh Kumar K
2026-07-23 11:02 ` Santhosh Kumar K
2026-07-23 11:02 ` [PATCH v6 02/17] spi: dt-bindings: add spi-phy-pattern-partition property Santhosh Kumar K
2026-07-23 11:02 ` Santhosh Kumar K
2026-07-23 11:02 ` [PATCH v6 03/17] spi: parse spi-max-post-config-frequency-hz into post_config_max_speed_hz Santhosh Kumar K
2026-07-23 11:02 ` Santhosh Kumar K
2026-07-23 11:02 ` [PATCH v6 04/17] spi: spi-mem: teach spi_mem_adjust_op_freq() about post-config ops Santhosh Kumar K
2026-07-23 11:02 ` Santhosh Kumar K
2026-07-23 11:34 ` sashiko-bot
2026-07-23 11:02 ` [PATCH v6 05/17] spi: spi-mem: add execute_tuning callback and spi_mem_execute_tuning() Santhosh Kumar K
2026-07-23 11:02 ` Santhosh Kumar K
2026-07-23 11:30 ` sashiko-bot [this message]
2026-07-23 11:02 ` [PATCH v6 06/17] spi: cadence-quadspi: move cqspi_readdata_capture earlier Santhosh Kumar K
2026-07-23 11:02 ` Santhosh Kumar K
2026-07-23 11:02 ` [PATCH v6 07/17] spi: cadence-quadspi: add DQS support to read data capture Santhosh Kumar K
2026-07-23 11:02 ` Santhosh Kumar K
2026-07-23 11:28 ` sashiko-bot
2026-07-23 11:02 ` [PATCH v6 08/17] spi: cadence-quadspi: add PHY tuning support Santhosh Kumar K
2026-07-23 11:02 ` Santhosh Kumar K
2026-07-23 11:33 ` sashiko-bot
2026-07-23 11:02 ` [PATCH v6 09/17] spi: cadence-quadspi: skip DDR PHY tuning for 2-byte-address ops (i2383) Santhosh Kumar K
2026-07-23 11:02 ` Santhosh Kumar K
2026-07-23 11:48 ` sashiko-bot
2026-07-23 11:02 ` [PATCH v6 10/17] spi: cadence-quadspi: refactor direct read path for PHY support Santhosh Kumar K
2026-07-23 11:02 ` Santhosh Kumar K
2026-07-23 11:41 ` sashiko-bot
2026-07-23 11:02 ` [PATCH v6 11/17] spi: cadence-quadspi: enable PHY for direct reads Santhosh Kumar K
2026-07-23 11:02 ` Santhosh Kumar K
2026-07-23 11:48 ` sashiko-bot
2026-07-23 11:02 ` [PATCH v6 12/17] spi: cadence-quadspi: enable PHY for indirect writes Santhosh Kumar K
2026-07-23 11:02 ` Santhosh Kumar K
2026-07-23 11:44 ` sashiko-bot
2026-07-23 11:02 ` [PATCH v6 13/17] spi: cadence-quadspi: reprogram CS timing on every chip-select switch Santhosh Kumar K
2026-07-23 11:02 ` Santhosh Kumar K
2026-07-23 11:49 ` sashiko-bot
2026-07-23 11:02 ` [PATCH v6 14/17] mtd: spinand: extract variant ranking logic into spinand_op_find_best_variant() Santhosh Kumar K
2026-07-23 11:02 ` Santhosh Kumar K
2026-07-23 11:02 ` [PATCH v6 15/17] mtd: spinand: negotiate optimal controller operating point before dirmap creation Santhosh Kumar K
2026-07-23 11:02 ` Santhosh Kumar K
2026-07-23 12:02 ` sashiko-bot
2026-07-23 11:02 ` [PATCH v6 16/17] mtd: spi-nor: extract read op template construction into helper Santhosh Kumar K
2026-07-23 11:02 ` Santhosh Kumar K
2026-07-23 11:02 ` [PATCH v6 17/17] mtd: spi-nor: run controller optimization before dirmap creation Santhosh Kumar K
2026-07-23 11:02 ` Santhosh Kumar K
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