From: Bin Meng <bin.meng@processmission.com>
To: QEMU <qemu-devel@nongnu.org>
Cc: Alistair Francis <alistair@alistair23.me>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org
Subject: [PATCH 14/26] hw/sd: cadence: Advertise 64-bit system bus support
Date: Thu, 23 Jul 2026 23:18:41 +0800 [thread overview]
Message-ID: <20260723151853.2143177-15-bin.meng@processmission.com> (raw)
In-Reply-To: <20260723151853.2143177-1-bin.meng@processmission.com>
PolarFire SoC software selects 64-bit ADMA descriptors for the Cadence
SDHCI controller. Advertise 64-bit system bus support so the existing
generic descriptor engine can execute those transfers.
Signed-off-by: Bin Meng <bin.meng@processmission.com>
---
hw/sd/cadence_sdhci.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/sd/cadence_sdhci.c b/hw/sd/cadence_sdhci.c
index 8476baf67f..39c6e5d101 100644
--- a/hw/sd/cadence_sdhci.c
+++ b/hw/sd/cadence_sdhci.c
@@ -54,6 +54,9 @@ static void cadence_sdhci_instance_init(Object *obj)
object_initialize_child(OBJECT(s), "generic-sdhci",
&s->sdhci, TYPE_SYSBUS_SDHCI);
+ object_property_set_uint(OBJECT(&s->sdhci), "capareg",
+ SDHC_CAPAB_REG_DEFAULT |
+ R_SDHC_CAPAB_BUS64BIT_MASK, &error_abort);
}
static void cadence_sdhci_reset(DeviceState *dev)
--
2.34.1
next prev parent reply other threads:[~2026-07-23 15:21 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-23 15:18 [PATCH 00/26] hw/riscv: Restore Microchip PolarFire SoC Icicle Kit firmware boot Bin Meng
2026-07-23 15:18 ` [PATCH 01/26] hw/riscv: pfsoc: Correct the L2LIM maximum mapped size Bin Meng
2026-07-23 15:18 ` [PATCH 02/26] hw/riscv: pfsoc: Map the L2 zero device window Bin Meng
2026-07-23 15:18 ` [PATCH 03/26] hw/misc: pfsoc: Support PolarFire SoC DDR training with newer version HSS Bin Meng
2026-07-23 15:18 ` [PATCH 04/26] hw/misc: pfsoc: Model L2 cache controller registers Bin Meng
2026-07-23 15:18 ` [PATCH 05/26] hw/riscv: pfsoc: Couple L2CC to L2-LIM Bin Meng
2026-07-23 15:18 ` [PATCH 06/26] tests/qtest: Add PolarFire SoC L2CC coverage Bin Meng
2026-07-23 15:18 ` [PATCH 07/26] hw/sd: sdhci: Migrate the Host Control 2 register Bin Meng
2026-07-23 15:18 ` [PATCH 08/26] hw/sd: sdhci: Accept version 4 enable without UHS-I Bin Meng
2026-07-23 15:18 ` [PATCH 09/26] hw/sd: sdhci: Use version 4 system address for SDMA Bin Meng
2026-07-23 15:18 ` [PATCH 10/26] hw/sd: sdhci: Support version 4 ADMA 64-bit addressing Bin Meng
2026-07-23 15:18 ` [PATCH 11/26] hw/sd: sdhci: Resume version 4 SDMA at buffer boundaries Bin Meng
2026-07-23 15:18 ` [PATCH 12/26] hw/sd: sdhci: Run ADMA independently of MMIO Bin Meng
2026-07-23 15:18 ` [PATCH 13/26] hw/sd: sd: Keep high-capacity memory blocks at 512 bytes Bin Meng
2026-07-23 15:18 ` Bin Meng [this message]
2026-07-23 15:18 ` [PATCH 15/26] hw/misc: pfsoc: Model PolarFire SoC serial number service Bin Meng
2026-07-23 15:18 ` [PATCH 16/26] hw/rtc: Add PolarFire SoC RTC model Bin Meng
2026-07-23 15:28 ` Conor Dooley
2026-07-23 15:55 ` Bin Meng
2026-07-23 15:58 ` Conor Dooley
2026-07-23 16:07 ` Bin Meng
2026-07-23 15:18 ` [PATCH 17/26] hw/riscv: pfsoc: Add PolarFire SoC RTC to Icicle Kit Bin Meng
2026-07-23 15:18 ` [PATCH 18/26] tests/qtest: Add PolarFire SoC RTC coverage Bin Meng
2026-07-23 15:18 ` [PATCH 19/26] hw/misc: pfsoc: Honor PolarFire service notification requests Bin Meng
2026-07-23 15:18 ` [PATCH 20/26] hw/riscv: pfsoc: Correct PolarFire SoC DDR aliases Bin Meng
2026-07-23 15:18 ` [PATCH 21/26] hw/riscv: pfsoc: Fix Icicle Kit RAM size at 2 GiB Bin Meng
2026-07-23 15:18 ` [PATCH 22/26] hw/riscv: pfsoc: Fix Icicle Kit hart count at five Bin Meng
2026-07-23 15:18 ` [PATCH 23/26] docs/system/riscv: Document Icicle Kit HSS boot Bin Meng
2026-07-23 15:18 ` [PATCH 24/26] docs/system/riscv: pfsoc: Document CLINT topology for direct Linux boot Bin Meng
2026-07-23 15:18 ` [PATCH 25/26] tests/functional/riscv64: Add Icicle Kit firmware boot test Bin Meng
2026-07-23 15:18 ` [PATCH 26/26] MAINTAINERS: Add PolarFire SoC Icicle Kit maintainer Bin Meng
2026-07-23 15:29 ` Conor Dooley via qemu development
2026-07-23 16:51 ` Markus Armbruster
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