From: sashiko-bot@kernel.org
To: "Mohamad Raizudeen" <raizudeen.kerneldev@gmail.com>
Cc: linux-pci@vger.kernel.org
Subject: Re: [PATCH v2] PCI: Fix 32-bit config write in Intel RP MPC ACS quirk
Date: Thu, 23 Jul 2026 17:18:15 +0000 [thread overview]
Message-ID: <20260723171834.17FFF1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260723171203.4892-1-raizudeen.kerneldev@gmail.com>
> The pci_quirk_enable_intel_rp_mpc_acs() reads a 32 bit DWORD from the
> MPC register, sets bit 26 (INTEL_MPC_REG_IRBNCE), but it writes it back
> using pci_write_config_word().
>
> Because bit 26 resides in the upper 16 bits of the 32 bit register, a 16
> bit write to offset 0xd8 completely drops the newly set bit. The quirk
> logs that it is enabling IRBNCE, but the hardware never actually
> receives the command.
>
> Fix this by using pci_write_config_dword() to ensure the full 32 bit
> value is written back to the hardware.
>
> Fixes: d99321b63b1f ("PCI: Enable quirks for PCIe ACS on Intel PCH root ports")
> Signed-off-by: Mohamad Raizudeen <raizudeen.kerneldev@gmail.com>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260723171203.4892-1-raizudeen.kerneldev@gmail.com?part=1
prev parent reply other threads:[~2026-07-23 17:18 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-23 17:12 [PATCH v2] PCI: Fix 32-bit config write in Intel RP MPC ACS quirk Mohamad Raizudeen
2026-07-23 17:18 ` sashiko-bot [this message]
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