[PATCH v13 4/5] dt-bindings: timer: dwc: Update resets property items

[dongxuyang@eswincomputing.com]

From: Xuyang Dong <dongxuyang@eswincomputing.com>

The DesignWare DW_apb_timers IP has two active-low reset inputs:
presetn resets the register interface logic in the pclk (bus) domain,
and timer_N_resetn resets the counter/timer logic in the timer_N_clk
domain. The existing snps,dw-apb-timer binding only describes one.

Update snps,dw-apb-timer binding to allow up to two reset lines,
matching the hardware capabilities of the DesignWare IP family.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com>
---
 .../devicetree/bindings/timer/snps,dw-apb-timer.yaml         | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
index d33c9205a909..4d30cd01ac65 100644
--- a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
+++ b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml
@@ -25,7 +25,10 @@ properties:
     maxItems: 1

   resets:
-    maxItems: 1
+    minItems: 1
+    items:
+      - description: Timer ticks reference (timer_N_resetn) reset
+      - description: APB interface (presetn) reset

   clocks:
     minItems: 1
--
2.34.1