Re: [PATCH v3 4/6] clk: qcom: Add Nord display clock controller support

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Missing `clk_alpha_pll_postdiv` object for `PLL1_OUT_EVEN`, resulting in incorrect parent aliasing.
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--- Patch [4]: [PATCH v3 4/6] clk: qcom: Add Nord display clock controller support ---
commit 15bad88e0e41a7dac6339581fa90741a6515e990
Author: Taniya Das <taniya.das@oss.qualcomm.com>

clk: qcom: Add Nord display clock controller support

Add support for the display clock controllers (DISPCC) on the
Qualcomm Nord platform.

> diff --git a/drivers/clk/qcom/dispcc0-nord.c b/drivers/clk/qcom/dispcc0-nord.c
> new file mode 100644
> index 0000000000000..835aba1596136
> --- /dev/null
> +++ b/drivers/clk/qcom/dispcc0-nord.c

[ ... ]

> +static const struct parent_map disp_cc_0_parent_map_7[] = {
> +	{ P_BI_TCXO, 0 },
> +	{ P_MDSS_0_DISP_CC_PLL1_OUT_MAIN, 4 },
> +	{ P_MDSS_0_DISP_CC_PLL1_OUT_EVEN, 6 },
> +};
> +
> +static const struct clk_parent_data disp_cc_0_parent_data_7[] = {
> +	{ .index = DT_BI_TCXO },
> +	{ .hw = &mdss_0_disp_cc_pll1.clkr.hw },
> +	{ .hw = &mdss_0_disp_cc_pll1.clkr.hw },
> +};

[Severity: Medium]
Will this cause the Common Clock Framework to miscalculate the frequency
if the bootloader leaves the hardware configured to select the OUT_EVEN
parent?

Because both OUT_MAIN and OUT_EVEN alias directly to the main PLL hardware
object without a post-divider object, it appears the CCF will read the
undivided main PLL rate for both. This could result in reporting a
frequency higher than reality, potentially causing downstream display
pipeline underflows or glitches during splash screen handoff.

Does there need to be a separate clk_alpha_pll_postdiv object to
properly model the OUT_EVEN divider?

[ ... ]

> +static const struct parent_map disp_cc_0_parent_map_8[] = {
> +	{ P_BI_TCXO, 0 },
> +	{ P_MDSS_0_DISP_CC_PLL0_OUT_MAIN, 1 },
> +	{ P_MDSS_0_DISP_CC_PLL1_OUT_MAIN, 4 },
> +	{ P_MDSS_0_DISP_CC_PLL1_OUT_EVEN, 6 },
> +};
> +
> +static const struct clk_parent_data disp_cc_0_parent_data_8[] = {
> +	{ .index = DT_BI_TCXO },
> +	{ .hw = &mdss_0_disp_cc_pll0.clkr.hw },
> +	{ .hw = &mdss_0_disp_cc_pll1.clkr.hw },
> +	{ .hw = &mdss_0_disp_cc_pll1.clkr.hw },
> +};

[Severity: Medium]
This struct has the same aliasing of OUT_EVEN to the main PLL hardware as
disp_cc_0_parent_data_7 above.

Could this also miscalculate the mdss_0_disp_cc_mdss_mdp_clk_src frequency
if inherited from the bootloader?

(Note: This exact same pattern appears in drivers/clk/qcom/dispcc1-nord.c
for disp_cc_1_parent_data_7 and disp_cc_1_parent_data_8 as well).

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Sashiko AI review · https://sashiko.dev/#/patchset/20260724-nords_mm_v1-v3-0-32b45232217f@oss.qualcomm.com?part=4